Address FinFET test challenges
A promising solution to FinFET test concerns is cell-aware ATPG (automatic test pattern generation) technology. This is true primarily because cell-aware ATPG is based on identifying possible defect locations and converting them into faults that ATPG can target. When a new technology is introduced, the physical design of the cell libraries can be automatically characterized for cell-aware defects specific to that technology. This specialized fault modeling, which can include cell-aware models as well as any user-defined models, is enabled by a user-defined fault model (UFDM) file. The result of the cell-aware characterization process is a cell-aware UDFM model for use in ATPG on any design that uses the cell library (see Figure 1). Thus, cell-aware test is well suited to address the uncertainty related to defects and test when new technologies, like FinFET, are introduced.
Figure 1. The automated cell-aware characterization process. The physical design of each cell within a technology library is analyzed to find potential defect locations. Then an analog simulation is performed to determine the input values necessary to detect the potential defects, which is turned into a fault model for ATPG.
Cell-aware test has already been proven to uniquely detect static and dynamic defects that are missed by traditional stuck-at and transition patterns. In published results, physical failure analysis confirmed that the uniquely detected defects were inside the cell. Further analysis proved that the defects were not detected by traditional tests with full coverage of traditional fault models (see “Finding fault with traditional test pattern types”).
FinFET technology uses a physical structure with fins that could produce more subtle defects than do traditional gates. This is especially true for FinFET devices with multiple fins between the source and drain. If a defect occurs within just one of the fins, then a more subtle effect on the gate operation will result (see Figure 2). Therefore, instead of only modeling a defect at one lumped sum gate and static defect resistance, cell-aware characterization allows us to simulate the representative leakage and drive defects. They can be modeled as multiple fins or, since cell-aware characterization allows several resistance values to be used in the analog simulation, as a traditional gate with varying resistance if that effectively represents the subtle defects within a fin.
Figure 2. Diagram of one FinFET with three fins. The effect of a leakage defect (top curve) and a drive defect (bottom curve) on the gate are shown. A defect within a traditional gate might be sufficiently modeled as a resistance, as shown with the blue resistances. The top (blue) voltage versus time curve show a notable impact in performance compared to a fully functional gate, shown in the bottom (black) curve. The middle (red) curves show the potential for more subtle defect impact.
Cell-aware test provides a powerful method to directly characterize defects based on the FinFET layout and analog properties. This ensures that your test patterns can detect static and dynamic defects that could be missed by traditional tests.
As FinFET technology develops, there is also lot of interest in being able to quickly analyze what types of defects are occurring. Using cell-aware characterization of defect locations can be used in reverse for diagnosis. When a defective part is detected, scan diagnosis tools identify the root cause of the defect, and yield analysis tools find the most important systematic defects to investigate. However, until now, the scan diagnosis resolution was only able to describe defects inside of cells as general “cell-internal” defects, but without more specific resolution. Using the principles of cell-aware test, scan diagnosis can map cell input values that detected the failure into an internal defect location within the cell. These two uses of cell-aware test will be essential to both ATPG and failure diagnosis for designs using FinFET technology.
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