Comparing flat ATPG and hierarchical tests
Traditional flat ATPG is simple because the automatic test pattern generation session is only performed on the single, final, netlist. Flat ATPG implies that the design is complete and the ATPG session is performed on the entire design at the same time as one “flat” view. However, for designs that are too big to perform flat ATPG, test engineers often turned to hierarchical DFT to manage compute resources and runtimes. The basic hierarchical DFT methodology involves designing cores with scan wrappers so that they can be tested independent of their context in the top-level design.
Then at the top level, the block is accessed in a test mode that routes all IC test ports to the block scan channels for ATPG and testing. This not only helps with compute resource memory but also improves the run time, since the blocks not being tested can be omitted from the design view used for ATPG of the block under test. In addition, hierarchical test lets you take into consideration the variations of pattern types, pattern counts, etc. between blocks.
Even hierarchical DFT without much automation support can give you over two times improvement in test application time. But now, newer automation capabilities have improved hierarchical test significantly, and make it an attractive option for many designs. New DFT tools can create graybox models of the blocks, which act as very small block images that can be used for top-level test rules checking and for interconnect test between the blocks (see Figure 1).
Figure 1. Wrapper chains allow blocks/cores to be tested independent of surrounding logic. Graybox models include minimal logic and wrappers to facilitate a small image in the top level design for interconnect test between the blocks.
Unlike flat test, hierarchical test focuses test insertion and ATPG on the block-level design. So, it does not need the design to be complete. With recent pattern retargeting automation, you can look at hierarchical test as a plug-n-play approach compared to traditional custom design (see Figure 2).
Figure 2. Pattern retargeting takes the independently generated patterns and retargets them to be applied at the IC level.
Hierarchical testing, like general plug-n-play methodologies, requires some additional work to ensure that a block is compliant with top-level design protocols. There are additional DFT logic insertion requirements that are not needed with flat ATPG. First, scan wrappers must be added to the blocks so they can be tested independently. Second, you need to add a top-level test access mechanism (TAM) to port the device IO to the block being tested. However, the benefits of hierarchical test are substantial, as with many other plug-n-play approaches.
For very large designs, hierarchical test is a necessity. However, the benefits are significant enough that many designers are adopting it even when they are not forced to by the size of the design. Because ATPG is performed at the block level, it works on much smaller designs—often an order of magnitude smaller—than the full top-level flat design. As a result, hierarchical ATPG runs are often an order of magnitude faster and the compute resources an order of magnitude smaller. Furthermore, if a block is used multiple times in the design, then ATPG only needs to be performed on that block one time. The same block patterns can be retargeted to any instantiations of the block in that design, or even in other designs.
For many test engineers, the most important aspect of hierarchical test is the greater predictability compared to flat ATPG. With flat ATPG, you perform ATPG experiments on individual blocks to make sure they have reasonable coverage, but then discard all that work. Even after doing block-level experiments, the final flat ATPG still presents some uncertainty until the design is complete because of issues created by how blocks are embedded and how they interact with each other. Hierarchical test reduces risk because the ATPG performed at the block level is directly retargeted and reused in the top-level design. Any problems that result from ATPG are found early in the design process when the block ATPG is performed. Similarly, if an ECO is required, then only the block with the change needs to have patterns regenerated. In flat ATPG, the entire ATPG process must be re-run for any ECO.
- Cell-aware ATPG test methods improve test quality
- Thorough test means testing through the RAM
- How to generate test patterns to detect FinFET defects
- DFT strategy for ARM processor-based designs
If you liked this feature, and would like to see a collection of related features delivered directly to your inbox, sign up for the Test & Measurement newsletter here.