Hierarchical test improves pattern application efficiency
For over 15 years, I've been a big proponent of hierarchical test. Hierarchical test is the commonly used term for creating DFT (design-for-test) features and test patterns at lower level circuit blocks that are somehow reused at the top level. The obvious advantage of hierarchical test is that the DFT and pattern generation can be performed on designs that are much smaller than the full top-level netlist. This provides an order of magnitude improvement in ATPG (automatic test pattern generation) run time and workstation memory requirements.
Hierarchical test also moves the vast majority of the DFT and ATPG work earlier in the design cycle, before the top-level design is complete. But there are also significant, though non-intuitive, improvements in test application time (the actual time on the tester when in production) by reducing the total number of test cycles in the pattern set.
While hierarchical DFT isn’t new, in the past it typically required that the full high-level design was complete, then you could test one block in the top-level design while all the other blocks are black-boxed. Special wrapper scan chains added at the boundary of the block being tested let it be tested in isolation. This method greatly improves the run time and workstation memory requirements. It still, however, requires you to have a complete top-level netlist prior to creating patterns. Plus, patterns created previously are used exactly as they were constructed during ATPG (i.e. generated and applied from top level pins); they can't be easily combined with other similarly generated patterns in parallel.
Fortunately, the automation around hierarchical test has significantly improved in recent years. You no longer need to wait until the top-level design or TAM (test access mechanism) is complete; all the block DFT work and ATPG can be completed with only the block available so the DFT effort can be performed earlier in the design process.
Block-level patterns and design information are saved as plug-and-play pieces that can be reused in any design. A top-level design is never needed in this flow in order to generate the block-level patterns. You only need block data to verify that the block patterns can be effectively retargeted in the top-level design and that the top-level design can be initialized such that the block being tested is accessible. Various block patterns are generated independently for each different block, but if the top-level design enables access to multiple blocks in parallel, then the patterns can be merged together automatically when retargeting to the top-level design.
The reason why ATPG and workstation memory is so much more efficient with hierarchical test compared to top-level flat ATPG is clear, but many people assume that top-level pattern generation for the entire chip in one ATPG run is more efficient for test time than testing blocks individually. In fact, hierarchical test is often 2x more efficient than top-level test. I’ll try to describe why with an example.
Figure 1 shows two approaches to test an IC. For each block we maintain a 200x chain-to-channel ratio. Thus, in the top-level ATPG case 800 chains with 4 channels results in a 200x compression ratio. However, in the hierarchical case there are 12 channels available for each core, so to maintain 200x compression ratio we would have 2400 chains. These chains would be 1/3 the length of the chains in top-level ATPG cores.
Figure 1. Flat ATPG tests all cores in parallel. In this case, core 1 requires fewer patterns than core 3. After 1000 patterns are applied, the four channels used for core 1 are useless bandwidth.
Top-level ATPG pattern count will be dictated by the block with the largest number of patterns. In this case, the tester cycles will be equal to
The hierarchical ATPG will run each block sequentially in this case. So each block can use all 12 channels and would have 2400 internal chains.
If each core has the same number of scan cells, then we get this comparison:
For flat ATPG
for hierarchial ATPG.
So in this case, hierarchical test is 60% of the time required for that of top-level flat ATPG.
In hierarchical ATPG, the bandwidth of all channels are used on one block at a time. Thus, more chains can be used on each block to maximize the channel bandwidth. This can significantly improve DFT efficiency.