Three predictions on the state of signal integrity
Based on discussions at DesignCon 2016 and since, I have three predictions about major changes ahead for high speed serial link systems.
Roll out of 28 Gbps systems will be slower than expected.
I hear that the semiconductor companies producing the CMOS devices—ASIC, FPGA or custom—are doing fine producing the silicon with acceptable performance at 28 Gbps. Figure 1 is an example of a very clean eye from a 28 Gbps TX (transmitter).
Figure 1. Today's silicon can product clean signals at 28 Gbps, at least at the transmit end.
Semiconductor manufacturers' ability to sell to end users designing and manufacturing systems operating with 28 Gbps links is, however, limited by the their ability to support these customers.
A link operating at 28 Gbps, NRZ (non-return-to-zero), has to be designed with everything working almost perfectly. This data rate pushes the limits such as: low Df materials, smoother copper, wide enough lines, equalization tuned to the limit of recovering -25 dB of insertion loss, minimal reflections, via stubs shorter than 15 mils, channel-to-channel cross talk less than -50 dB, and line-to-line skew less than 6 ps over as long as 20 in.
By themselves, each item is possible to engineer, but all of them at the same time in the same channel requires solid engineering and analysis. Not every design team is capable of this task. When the channel does not work, who do they call? The silicon provider.
I hear that with a limited number of experienced support application engineers, the silicon providers are focusing on their large, high-end OEM customers and are limiting their sales based on which customers they have the resources to support. This may be a business opportunity for consulting engineering teams to work with silicon providers to support their customers and increase the design wins and sales of 28 Gbps capable silicon.