Design Con 2015

Questions on PC boards for EMC mitigation

-July 15, 2013

Thanks for all the great questions presented following my recent EMC webinar, sponsored by Rohde & Schwarz and hosted by UBM TechOnline. If you missed the webinar, you may go here to download a copy of the slides and listen to the webinar "on-demand". As I mentioned in the previous posting, I've grouped them by topic and will be answering them all the best I can. Be advised that for many questions pertaining to EMC, the best answer is, "it depends", so there may not be one answer for all cases. I'll try to include my assumptions in the answers. The questions have been edited for clarity.

This posting will address questions on PC boards and related topics.

Q. Will you address analog and digital ground separation and when you tie them together to chassis ground.

A. Good question. Currently, there is some debate as to whether there should be separate ground planes or just a single one. First, let me state up front that I prefer to call these planes "signal return" and "power return" planes, rather than ground planes. Referring to them as signal and power returns are more accurately descriptive and remind the designer that currents flow in loops. Very often we designers inadvertently divert the return current path over a longer route, which can cause radiated emissions and other immunity issues. Remember, at frequencies above 100 kHz, the return current wants to flow along the path of least impedance. This is usually directly under the signal or clock trace.

So, your question boils down to controlling the paths of analog and digital return currents. By splitting the analog and digital return planes, noisy digital return currents will stay out of the sensitive analog area. Obviously, one wouldn't want to run digital signal traces across isolated analog areas, as this would also contaminate  the analog area. The latest thinking, however (Todd Hubing, Clemson University) is that it's best to keep the return planes as a single plane and be careful about routing the signal traces (keeping in mind the corresponding return currents), so they don't cross the A/D boundary. The two planes are generally connected together at the PC board power connector.

Q. What are stitching capacitors? How do I select stitching capacitors? In your early/first example of signal and two power planes how does one add stitching caps - looking for the physical implementation.

A. Stitching capacitors simply allow a path for return currents to get back to the source when crossing multiple planes with differing potentials - for example, power and signal return planes. They need to be located as closely as possible to where the high frequency trace penetrates the planes. The value is not critical, but should present a low impedance at the frequency in question (plus harmonics). Most designers use 1 to 10 nF. I explained this in more detail here.

Q. In the slides with the via, where is the ground plane? On both sides? You just show arrows.

A. This is explained more clearly here.

Q. How many layers do you recommend for solving EMC/EMI issues on PCB? E.g. we may define different power and ground layers for analog and digital signals respectively.

A. From an EMC standpoint, eight, or more, layers has proven best. The problem with four or six-layer board designs is that it becomes very difficult to define a solid low-impedance return path when running high speed signals and clock traces through multiple power/return planes. You also want the power and signal/power return planes to be as close together as possible and sometimes this is difficult to manufacture.

Q. In what case, do we need to separate analog and digital ground?

A. This was at least partly answered above, but let me just say that the reason we might want to separate analog and digital return planes is to keep noisy digital signals from contaminating sensitive analog circuits. The same might hold true if the analog circuitry might be very noisy - for example motor control switching logic.

Q. A lot of designers like to "star" the grounds. in this sense, a lot of digital traces cross planes. what would would you recommend in this type of scenario?

A. I'm not sure a completely understand your question, so if my answer is unclear, please respond in the "comment" section of the blog posting. A "star" ground usually implies (or is another name for) a "single-point" ground. At high frequencies (say, above 100 kHz), so-called single point grounds are near impossible to achieve, due to inductive and capacitive coupling. Basically, there are too many other "sneak" paths. So, my recommendation is normally to design multiple grounding schemes. Single point and multiple grounding usually applies to system grounding, not PC boards, so hence, my confusion. Assuming the plane to which you're referring is a signal return layer, then we want the signal traces crossing over it in order to minimize the impedance to the return currents.

Q. Is multiple shorting of ground planes a good practice?

A. Yes, especially if high frequency traces are referenced to both return planes. Multiple vias will provide multiple paths back to the source. There's another phenomenon to keep in mind. At really high frequencies (above 500 MHz into the GHz region), the power and power return planes can form a cavity resonance and cause radiated emissions. Adding a pattern of stitching capacitors can help break up this resonance. There are also experiments on the use of "lossy" bypass capacitors (high ESR) mounted around the board that serve to damp the resonances. Refer to Lee Ritchey's work for this technique.

Q. How effective is shorting of ground planes ... is direct shorting effective or through 0 ohm passives.

A. As we approach frequencies above 100 MHz, or so, series inductance can become significant. Therefore a classic via would work better than a zero-Ohm resistor, depending on the connecting traces. If you were careful, there may not be that much difference. Zero-Ohm resistors are certainly good for experimentation, but then I'd replace them with vias.

Q. A lot engineers struggle to believe a short PCB trace, which is a fraction of the wavelength, can radiate? How is this possible?

A. The general rule of thumb is that if a trace (or cable) is electrically 1/20th wavelength, or less, then it becomes a very inefficient radiating structure. As the length starts to approach a half-wavelength, then it becomes an efficient antenna. Bruce Archambeault wrote on this topic and I extended the concept by suggesting following up near field measurements with antenna measurements to confirm whether a structure radiates, or not. Remember the velocity factor of epoxy-fiberglass shortens the wavelength.

Q. On a multi layer board what is the best location for the ground plane layer?

A. This is one of those "it depends" questions. You can do either. Keep in mind that above all it is very important to keep the power and power/signal return planes closely spaced together in order to provide some built-in high frequency bypassing. In fact, 3-4 mils (for example, 3M's "C-Ply" material) will provide an excellent high frequency built-in bypass capacitance. So, keeping that in mind, this "power/ground" sandwich may be located anywhere. You can even use multiple P/G sandwiches in a board design. Some designers also like to design their boards with extra return layers on the top and bottom, along with a continuous via stitching in order to form a Faraday shield around the entire circuitry. This can reduce board emissions significantly. By how much? It depends(!), but I've seen reductions up to 18 dB!

Q. I was told to NEVER break a GND plane into separate digital & analog GND planes. But you can group the digital & analog circuits above the unbroken GND plane. Is this good EMC practice (i.e. never have separate digital & analog GND planes)?

A. See some of the discussion above. Theoretically, you should be able to run analog traces on one side of a return plane and digital traces on the other because skin effect makes the single copper layer look like two separate layers. Where the concept might fail is if you needed to penetrate from one side of the plane to the other for some reason. Then, I could see return currents possibly contaminating from one side to the other. The whole trick is to keep track of the return currents for every trace. Easier said than done.

Q. Can power planes (VCC) be used as reference planes for a return path.

A. Yes, but be careful to have a well-defined return path. You'll need to use stitching capacitors for this. Note that DDR3 memory requires that some signals be referenced to the power plane and some to the return plane. This is defined in the part specification.

Q. In EMI/EMC point, the series resistor is required even if the trace length is less (like less than 1 inch).

A. Not sure I completely understand your question. Are you referring to termination resistors in transmission lines? If so, "it depends". You'll need to use a simulator like Hyperlynx to analyze the path and routing of the transmission line.

Q. For cost, we want to use unshielded cables with differential low speed signals. Will we need chokes on board or can we get away with 0.001uF caps across the diff signals?

A. It depends what you mean by "low speed". I would first try the 0.001 uF capacitor, but have a "plan B" in mind. If there are other high frequency signals (say, greater than 20 MHz) on board, you'll likely have to add common-mode chokes.

Q. Which plane can be regarded as a good reference plane? Is it the ground plane? Thanks.

A. It depends, but generally, that's correct.

Feel free to add additional questions related to PC boards. I'll be posting additional questions asked during this webinar in later blogs.

If you missed the webinar, you may go here to download a copy of the slides and listen to the webinar "on-demand".

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