Pulsic: the bleeding edge of custom IC design

Brian Bailey - November 14, 2012

If you do custom chip design, you probably know Pulsic, an EDA company based in England that provides floorplanning, placement, and routing solutions for extreme design challenges at advanced nodes. Complementary to existing design flows, Pulsic works with companies that have traditionally preferred handcrafted design methods; it promises faster and higher-quality results compared with general-purpose EDA software solutions. Mark Williams, co-founder and CEO of Pulsic, recently spoke with EDN. Excerpts of that conversation follow, with a focus on analog and memory.

How did you come to start Pulsic?

A: I was one of the developers of our original core technology, and the founding team actually came out of a company you might remember: Racal-Redac. A couple of the founders were responsible for the world’s first shape-based router, which was back in 1985. The cornerstone of the company continues to be shape-based techniques. We have expanded the product line of the company to cover chip planning, placement, and routing for the whole custom spectrum. Today, we try to be the complete custom company, and what I mean by custom is everything that basically isn’t a standard RTL-to-GDSII digital ASIC flow.

So that’s how you compete against the big three?

A: We only compete against Cadence because, in the custom world, the golden standard has always been to do it by hand, in Virtuoso. Synopsys has been trying to break in on that monopoly with the Galaxy Custom Designer.

We live with Cadence and are in their connection program. In the memory market, this has been particularly good for us. Memory has unique custom requirements, which means you can’t really shoehorn it into an ASIC flow. For example, you have a 21:1 aspect ratio with two metals, highly resistive gates, etc. ASIC tools can’t do a good job of that, and we’ve developed specific custom tools to do a really good job in memory, and it’s been our mainstay; it’s been our cash cow. We’ve been very successful automating what was a manual approach to the layout of memory.

What are you investing in?

A: We are putting a lot of effort into transistor layout. Transistor layout in analog has long been seen as the Holy Grail of automation. Nobody has done a successful job of really automating analog layout. And truly it comes down to what we call precision design automation. It’s not a question of just automating a design in terms of getting it done in the analog market. The average designer will look at it and say, “OK, yeah, it’s placed and it’s routed, and it even meets my parasitics, my resistance capacitance,” but there’s no way the analog designer will take those results, because how it is laid out matters; it really is a handcrafted piece of work that the analog designers do. And getting an automated method or a methodology to give an analog designer a layout that he can [approve of], I would do that kind of layout by hand; that is what’s been the Achilles’ heel. But we are excited about some technology we’ve got in this space. We hope that by next year we will have place-and-route technology for the analog space that will really deliver what we believe will be full hierarchy layout for analog design. And of course, it’s got some killer interactive stuff in there, as well, that you have to have.

Analog hasn’t been scaling quite as nicely as digital for some time. What technologies are most people now using for custom analog?

A: A lot of custom analog is being done on older technologies. The reason many people are not moving to the newer nodes is the extra and more complex design rules and constraints that they have to consider (by hand), and this restricts them from moving. It’s a bottleneck. If there were more analog automation, you would see more analog designs rushing toward the newer technologies.

Will we ever get to a notion of analog synthesis?

A: Synthesis is not the right word for analog really, because it’s a schematic- driven environment. I don’t think we will get to a sort of high-level RTL description of analog in the near future, so realistically what you’re talking about is generating a layout from a schematic and doing everything thereafter.

So you don’t think that we’re ever going to be able to go from an analog behavioral language?

A: Maybe. I don’t foresee that anytime soon, though, no. You also have to see that we are a physical design company and not moving into the front end.

What advice would you have for somebody thinking of starting an EDA company?

A: Be realistic. If you are a virgin EDA start-up, like we were, don’t think that you can take a piece of technology to market and it will all fly. It won’t. Customers will shoot you down in flames, so you have to have a passion for it. You’ll have to work hard and develop continually to get to a point where your product really offers the advantages and returns so that customers will stop doing things the old way and take on your new technology.

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