Mindspeed visualizes an opening in the base-station market
The dual pressures of higher data bandwidth and media data types are changing networks from endpoint to core. And wireless networks, forced to shift from their rapid deployment of HSPA to LTE while simultaneously staggering under the blows of growing smart-phone use, are taking the brunt of the changes. That impact is altering the hardware in both base stations and backhaul networks.
One of the architectural features coming under pressure is the base station's baseband processor. The implementation of choice for this critical block in 3G days was either an array of DSP chips backed by massively expensive FPGA offload engines, or one of a few ASSPs. But Alan Taylor, director of marketing at Mindspeed, argues that neither of those approaches will scale to full LTE/WiMAX without rearchitecting. The FPGAs will have to move up to higher throughputs and to displace the DSPs, and the ASSPs will need a generational respin.
That makes an opening for a new player, Taylor claimed. Mindspeed, already a player in the VoIP and xDSL markets, jumped in Monday with its own new ASSP family, Transcede 4k. The initial chips, the 4000 and 4020, are 40-nm devices aimed at macro-, micro-, and pico-cell baseband processors handling 40-Mbit HSPA, LTE, or WiMAX traffic in both SIMO and MIMO environments.
To deal with the data rate and increased processing load, Mindspeed has chosen a heterogeneous multicore approach—perhaps the most ambitious of its kind—built on an ARM multi-layer AXI interconnect fabric. A central fabric connects processing and I/O clusters, which in turn may have their own internal fabrics.
The Transcede architecture comprises two processing clusters and two I/O clusters. A system cluster—the primary resource for system control and packet processing—contains both one quad-core and one dual-core ARM Cortex A9, united on a local AXI fabric with hardware accelerators for forward error correction and encryption, an elaborate DMA engine, cache, and a DDR2/3 DRAM interface. The second processor cluster, connected to the first through the chip's system-level AXI, holds 10 CEVA 1641 programmable DSP cores, 10 proprietary filter-processor cores, their local memory instances, another DMA engine, and another DRAM interface, all on another local AXI fabric. Altogether, the chip has 7 MBytes of user-accessible RAM and about 2 MBytes of non-user RAM, according to Taylor.
Two more clusters on the system AXI contain the expected collection of system I/Os, including a pair of Gigabit Ethernet ports, grouped around a local AMBA AHB bus; and a cluster of 10 high-performance SerDes lanes, multiplexed into a collection of controllers: two sRIOs, one PCIe gen II, and one CPRI.
The point of such an ambitious multicore architecture is to bring software-level programmability to LTE-level throughput. But that undertaking brings users face to face with the problem of programming a large heterogeneous multicore architecture for wirespeed operation. To crack the problem, Taylor said, Mindspeed has taken a new approach to modeling the system. The user-programmable computing loads are broken into tasks and coded in C. These tasks call a library of inter-task communication utilities that are based on a task control block convention. Actual task scheduling is done in a combination of hardware schedulers and software, something of a Mindspeed signature touch. But for the first time, the company is opening the task control mechanism to customers. The task manager also controls clock gating of the 26 processors, getting stated power down under 15W at 750 MHz.
To make debug feasible, Mindspeed has relied heavily on the internal debug monitors of the Cortex CPUs and the AXI busses. So developers will have considerable visibility into both code threads on the control processors and interprocessor traffic. Whether this access, plus the considerable software investment Mindspeed will have to make internally, will be sufficient to crack tightly coupled processing problems such as beamforming on a large multicore architecture while handling packet processing in the background of course remains to be seen. But the company has experience with the architectural concepts, it has three pre-silicon customers, claims to be sampling silicon now, and must be taken seriously in this market.