EDN’s 20th annual Innovation Awards Finalists

EDN Staff - February 18, 2010

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Category: Microprocessors
Finalist: MPC564xL high-reliability processor, Freescale Semiconductor

The MPC564xL family implements a new strategy for detecting critical faults in safety relevant blocks and provides major test capabilities in hardware to reduce the software overhead and typical board component count. Built-in Self Test (BIST) mechanisms are introduced for the cores, memories, crossbars, communication blocks and peripherals. The device is optimized to prevent common cause failures induced by clock or voltage supply issues—in mainstream lockstep devices where both channels of the "sphere of redundancy" execute the same software, such faults would not be detected. The MPC564xL family provides hardware blocks for detection of clock deviations as well as hardware monitors for main voltages.

The MPC564xL can be run in two statically configurable modes of operation giving designers flexibility when deciding which of the MPC564xL capabilities to optimize for their application. The two selectable modes of operation, which both support SIL3 and ASILD requirements, are: Lockstep operation, which provides a software environment for redundant processing and calculations and; Independent core operation (dual parallel mode) which provides a software environment for diverse processing and calculations to increase performance or to cross check for reliable operation.

For extended sphere of replication support, the MPC564xL goes beyond just the cores and adds other key hardware blocks to the "sphere of replication," such as; Crossbar, Memory Protection Units, Interrupt Controller, DAM, Software Watchdog Timer. The main benefit is the capability to detect single point failures which are typically higher rate soft errors not only in the cores but also in key sub-modules of the microcontroller.