Cadence fills out DFM flow in time for 45-nm design
By Michael Santarini, Senior Editor - September 11, 2007
Cadence Design Systems officially unveiled Monday at the CDNLive! conference its 45-nm IC design implementation and DFM (design for manufacturability) tool flow, which integrates into the Cadence lineup new technologies including a DFM predictor, an SSTA (statistical-static-timing-analysis) tool, and a critical-area-analysis engine, plus technologies from recent acquisitions of Praesagus and Clear Shape.
In back-to-back presentations at CDNLive!, Mike Fister, Cadence's president and CEO, and well-noted UC Berkeley Professor Alberto Sangiovanni-Vincentelli, The Edgar L. and Harold H. Buttner Chair of Electrical Engineering, outlined how designers using advanced process geometries are increasingly struggling to ensure that what they design is actually what gets manufactured.
With the rise in process variation and the need to bring more manufacturing data into the design flow for advanced processes, the IC design community is experiencing something similar to what PC and printer vendors faced in the early days of PCs, Fister said. Back then, a printer could not necessarily reproduce an image that appeared on a PC's display. The PC industry struggled with the problem for a while but finally solved it, coining the phrase "WYSIWYG" (what you see is what you get) along the way. Cadence purports that its new DFM flow for 45 nm will transfer that concept to the IC-design world. In fact, Cadence is using the term "WYDIWYG" (what you design is what you get) in a marketing campaign.
To back it up, Cadence, through acquisitions and internal development, has filled out its implementation and DFM tool flow for 45-nm designs. In particular, the company has added several new enhancements and tools to its Encounter GXL lineup.
The first is a new fast litho-estimator engine called Aura, which Cadence has added to its NanoRoute IC router. Mike McAweeney, Cadence's vice president of marketing for DFM products, said designers will employ a successive-refinement approach to get rid of lithography hot spots. A first run with NanoRoute, for example, may reveal hundreds of lithography hot spots, said McAweeney. Designers will then use the Aura technology to find the optimum IC topology to reduce the majority of lithography hot spots; Cadence claims Aura will reduce anywhere from 50% to 80% of the hot spots.
Designers will then move their design to Cadence's Encounter gridded router and use traditional methods to further reduce lithography hot spots. They will then use a new space-based routing engine borrowed from Cadence's full-custom Space Based router (that engine now comes standard in Encounter GXL) to correct the remaining lithography hot spots in the design's layout. Thus at the end of the routing cycle, designers will be able to pass a litho-friendly design to manufacturing.
The new estimation engine for the router technology draws on analysis tools Cadence gained in its acquisitions of Clear Shape and Praesagus, a deal it made with IBM for CAA (critical-area-analysis) technology, and from an SSTA tool it developed internally.
Cadence has renamed the acquired tools: ClearShape InShape is now called Litho Physical Analyzer, Clear Shape's Outperform is now called Cadence Litho Electrical Analyzer, and Praesagus' DVIP tool is now called CMP Predictor. The Litho Physical Analyzer and Litho Electrical Analyzer will provide Litho hotspot data for Aura, while the Praesagus tool will provide users with CMP simulation/detection to reduce dishing effects and find shorts related to dishing.
Cadence also officially announced that it has purchased a CAA engine from IBM that will handle all CAA functions for the Cadence 45-nm tool flow. The company declined to explain further details of that arrangement.
And last but not least, the company announced it has jumped into the SSTA market, offering the new statistical-timing-analysis capabilities in its Encounter GXL platform.
The new tool, Timing System GXL, which Cadence developed in house, will use a "sensitivity-based statistical timing method," said Rahul Deokar, product marketing director for the Encounter Platform Timing And Signal Integrity Group at Cadence. "On the transistor and cell side, budget parameters like length, width, and thickness of the transistor vary and lead to variations and delay on a device," Deokar said. "We capture the sensitivity of the delay to these underlying parameters. This is stored in a library. What we have done is extended our ECSM timing format to capture this sensitivity information and model this in the ECSM."
Deokar said device interconnect has similar budget parameters, such as length, width, and dielectric thickness, that lead to delay. "For interconnect, we've extended our QRC extraction system to be able to extract this information and generate statistical SPEF information," Deokar said. "When we do our statistical optimization, it is based on the sensitivity data we've captured on both the device side and interconnect side."
David Desharnais, product group director for P&R/analysis Encounter group at Cadence, noted that one of the reasons statistical-static-timing-analysis tools have thus far not taken off is that IC fabs and foundries have been reluctant to share critical static-timing data with SSTA tool providers. But Cadence announced that it has been working closely with a few IDMs and is working with both Altos Design Automation and Stratosphere Solutions to use their respective statistical-timing libraries and process-variability models in the new SSTA tool. Those companies are providing libraries with statistical parameters for transistors and interconnect in the extended ECSM (effective current source model) format.
One early customer of the SSTA tool is Japan's STARC (Semiconductor Technology Academic Research Center), and Cadence plans to announce another major SSTA tool customer later this week, Desharnais said.
Since it introduced its static-timing tool last year, Cadence has gained around 12% marketshare in the static-timing niche, according to Desharnais. The company claims to base these marketshare figures on EDAC quarterly reports and from its own research. If true, the marketshare would likely have come at the expense of Synopsys, which has traditionally held more than 90% of the market in static timing analysis.
Desharnais says the company hopes to further extend that marketshare grab with its new SSTA tool. It's evident that Cadence also hopes to grab a big share of 45-nm customers, as well.