Silicon intellectual property panel puzzles selection process

A panel discussion at DesignCon Wednesday afternoon showed just how little progress has been made in the silicon intellectual property (IP) market in the last five years. A discussion that—for many of the concerns expressed and the remedies proposed—could have taken place in any one of those years never the less produced a valuable harvest of hands-on data to go with its conventional wisdom.

Chaired by Virtual Socket Initiative (VSI) Alliance President Kathy Werner, the panel brought together foundry, ASIC, EDA, IP and OEM speakers to share their views. Many of these were familiar. If the IP is complex, select very carefully. If it is complex and not tested in silicon, select very, very carefully. But the gems were in the details of the discussion.

Bob Kirk, director of strategic marketing at AMI Semiconductor, spoke from the vantage point of an FPGA conversion shop, but made a point that was broader in its usefulness. “We encourage our clients when they are doing their initial FPGA design to choose third-party IP with migration in mind,” Kirk said. “That means to make sure that the IP is not only synthesizable for your chosen FPGA, but that it is available in the ASIC process—and the process variant—that you intend to end up in.”

Then Kirk added the telling point. This advice doesn’t just apply to designs that go into early production in FPGAs and then might later convert. It applies equally, he said, to projects that are ASIC designs from the outset but will use FPGAs for prototyping. It’s important that the IP be available for the FPGA and for the ASIC process—and that the design team understand the differences between the two instances—to prevent the FPGA prototype from becoming a whole separate design effort rather than a verification tool.

Mobashar Yazdani, senior engineer/scientist at Hewlett Packard, added another gem. He observed that generally people think of IP selection in terms of finding a hardware component that fits a hardware specification within a given price range. But as blocks grow larger and become subsystems, IP may cease to act like a hardware component, and may include driver software, test strategies, integration issues, legal issues and other considerations. For complex IP, Yazdani said, selection means optimizing a choice across all the boundaries spanned by the results of the decision.

Panelists pretty much agreed that a reasonable set of selection criteria based on the description of the IP, the deliverables, user experiences and reputation served as a good basis for evaluation of mature IP that has been in silicon already. But the situation can be quite different if a chip design team is working on the leading edge of an application area, so they know they will be the first users of the IP they choose—and may even be involved in its development.

“In cases like this, you have to be certain of an absolutely intimate relationship between your design team, the IP design team and the target foundry,” urged Walter Ng, Chartered Semiconductor senior director of alliances. “Not only do you and the IP developer have to work together, but that IP may have to go on very, very early shuttle runs at the foundry.”

A final gem lay in the observation made by several panelists that relationships carried enormous weight in IP selection. “Track record means an awful lot,” Ng said. “I admit this makes it very difficult for start-ups.” And that knowledge of track record is intimate.
“You get to know your providers very well—not just as a company, but as individual engineers,” Ng said. “If people move to a different company—and typically a whole design team will move at once—you will know about it.”

Yazdani seconded the personal level of these relationships. “There have been cases when we’ve switched IP suppliers when their lead designer moved to a different company,” he said.

The picture the panel painted was one in which IP functionality is still not a given, and there are still serious errors to be made in IP selection. But the scene did show the growing maturity and reputation of a few—mostly either large or very specialized—IP vendors. And it reflected how the ability to work at an engineer-to-engineer level with particular designers has emerged as a key decision factor in challenging IP selections.