AMD Unleashes Torrenza Strategy
By Jessica Davis - June 1, 2006
Audiocast: Phil Hester, chief technology officer at AMD, talks about the company's technology road map. Click here to listen.
SAN JOSE -- AMD provided details for its new platform code-named Torrenza that will implement the company’s next generation architecture due in the first half of 2007.
The processor maker offered the preview during an analyst and press technology day here today and also provided a broad picture of the company’s strategy in design, manufacturing, capacity growth, and plans for market share gains and technology innovations for various markets.
AMD’s Torrenza platform is the fulfillment of the company’s hints at an open and extensible architecture for its chips. Chuck Moore, AMD senior fellow, first disclosed the idea of close integration with co-processors to Electronic News at the Spring Processor Forum, saying that the technology could eventually be integrated even further onto the processor itself.
The architecture allows partners to use AMD’s HTX slot to closely integrate co-processors or accelerators for applications such as media encoding and decoding, XML, gaming, scientific uses, and other applications, said Marty Seyer, senior VP of AMD’s commercial business segment, during his presentation at the event today. Seyer offered examples showing how different computing appliances could take advantage of the customization. For instance, the network processing space might use content or security processing devices while enterprises might use Java or XML and telecommunications companies might want a co-processor for VoIP.
“Torrenza gives the industry the first x86 customer-centric innovation platform,” he said.
The Torrenza platform calls for integration between the co-processor and processor, and eventually calls for putting the two components in the same package. Ultimately AMD will integrate the co-processors/accelerators on chip.
“We will integrate them on the CPU die itself when it makes sense,” said CTO Phil Hester in his presentation. “It is important to lay the groundwork for this today and watch the technologies as they evolve and integrate from left to right as it makes sense.”
AMD is ramping up its design efforts for these new platforms and the platforms to come with “parallel design efforts,” said Hester. These efforts will use modular building blocks that allow engineers to reuse functional blocks from one generation to the next, he said.
Examples of such blocks are the compute core, memory controller, HyperTransport, I/O interfaces, clocks, and various level caches. Hester also said there would be an “other” category that could be filled by the co-processor or accelerator blocks described in the Torrenza platform.
“There is no performance penalty [for using this design technique] if you do it right up front,” said Hester, during a question and answer session. “You have to build these building blocks to be plugged together like Legos.”
AMD also provided more detail on its plan for capacity expansion. The company announced plans to invest $2.5 million in its Dresden fab earlier this week. That capital spending is part of the company’s overall plan to increase its total capacity by four times over its current level by 2009 with an eye to serving a third of the x86 market by 2008.
The capacity expansion plans rely on the Dresden investments, the company’s relationship with Chartered, as well as the test and assembly “shells” in Singapore Penang and Suzhou that are ready for expansion.
AMD has also focused on improving efficiencies in its manufacturing operation, said Daryl Ostrander, senior VP for logic technology and manufacturing in his presentation.
“Our industry needs to think differently about the role of manufacturing,” he said. “We are a wasteful industry.” To address that, Ostrander said that AMD has implemented a new discipline it calls “Lean” which focuses on the value chain and eliminating steps that do not add value.
“We’ve been working on Lean for about a year, and since we’ve started we’ve achieved continuous cycle time improvement of 20 percent. Fab wafer output has increased by 47 percent during this time,” he said. “To increase cycle times without investing new capital is a significant accomplishment.”