Panel looks ahead to nanotechnology in sublithograhic semiconductors
Process shrinks will start to push CMOS lithography to the breaking point in 10 to 15 years, so IC vendors today are studying nanotechnology, including structures such as carbon nanotubes, as a possibility for augmenting or even replacing CMOS as the fabric for sublithographic semiconductors.
That's the message top nanoelectronics researchers from academia and large semiconductor firms delivered last week in San Jose at a panel during the ISQED (IEEE International Symposium on Quality Electronic Design) conference.
Nanotechnology is still in its infancy—so new that researchers still debate the definition of the term. One panelist said that as it relates to semiconductors, nanotechnology is just a fancy synonym for advanced chemistry, while another said it is synonymous with advanced materials science.
The labs of semiconductor firms like IBM, Texas Instruments, Infineon, and Hitachi, along with academics, are conducting the bulk of the research in the space. Their well-funded efforts are looking for the breaking points of traditional planar CMOS and what new technologies can keep it going.
The debate of the day in the nanoelectronics research community revolves around which method of nanotechnology best suits sublithographic semiconductors. Intel researcher Vivek De said that below the 45-nm node, companies are going to start considering nonplanar device structures such as tri-gate and FinFET thin-body transistors. Below 22 nm, roughly in the year 2011, is when nanotechnology will enter the picture, De said ( to see a slide displayed during the panel, which describes Intel's vision of when nanotechnology will enter the picture).
Panelists agreed with the prevailing wisdom that at that point, the photoresist method used in IC fabrication will be supplemented or even supplanted by a process in which companies place carbon nanotubes on a substrate and then, with doping methods, coax the nanotubes to align themselves at the atomic level into transistors and traces.
Doing so will bring vast power, density, and reliability savings compared with conventional advanced CMOS processes, the panelists indicated.
Carbon nanotubes have a diameter of 0.4 to 50 nm and have characteristics that make them ideal for semiconductors, said Infineon's Franz Kreupl. Noteworthy electrical conductivity characteristics of carbon nanotubes, Kreupl said, include ballistic transport, high-k dielectric compatibility with no dangling bonds, symmetrical device characteristics for n- and p-type, and doping by charge transfer with no impurity scattering. Nanotubes also offer excellent thermal, chemical, and mechanical stability, he said. Carbon nanotubes and even finer nanowires have been proven to work on a limited scale, he added.
Panelist Andre DeHon, a computer-science professor at Caltech, showed attendees a rough but real example of how sublithographic programmable-logic arrays can be interconnected using nanowires.
Getting the carbon nanotubes and wires to line up is like herding sub-microscopic cats. "It is very difficult to do," Kreupl told EDN.
Stanford University professor Philip Wong said that while early studies indicate that nanotubes and nanowires hold great promise for the future of semiconductors, researchers understand only a small fraction of their properties.
Kreupl and other panelists said that if and when the technology does become commercialized, it will likely appear first in hybridized form alongside CMOS. And it will first be applied to memory structures before finding use in logic devices.
Hitachi's Kazuo Yano suggested the technology should target niches that hardware and software cannot currently achieve. Yano cited MEMS (microelectromechanical system)-based accelerometers used in airbags as an example.
Robert Doering, technology strategy manager at Texas Instruments, said that ultimately, yield issues and the cost per function will determine what materials find use in next-generation semiconductors.
"Will there be hidden gotchas that kill the yield, defect- or parametric-wise?" Doering asked. "And ultimately, we have to worry about the cost of implementation. How far we scale something in CMOS and whether we go to extreme forms of CMOS, will depend on cost per function. If we can't drive cost per function down any more, then we probably won't go there."