EDA startup targets IC thermal hot spots
By Michael Santarini, Senior Editor - June 12, 2005
As chips become smaller and faster while running more circuitry on less power, the chance of heat adversely affecting power, performance, and overall lifecycle grow. Aiming to address this threat, EDA startup Gradient Design Automation will introduce both itself and a thermal-analysis technology called FireBolt this week at the Design Automation Conference.
Gradient is a nine-person company that consists of EEs, software engineers, and experts in device physics and heat transfer. EDA veteran Rajit Chandra, who sold his previous company Moscape to Magma Design Automation in 2000, founded and heads Gradient.
After selling Moscape, Chandra became interested in the IC power problem and noticed a plethora of startups gearing up to address the area, many of which are announcing products at this year's DAC. So Chandra chose to leapfrog into the next logical problem related to power: IC thermal analysis.
"Back when I was at Intel, we used to say 'What is the chip temperature going to be at this power,'" Chandra said. "Now we are saying 'What is the temperature so we can better understand what the leakage is going to be.' Suddenly temperature is a driver rather than an effect of what else is going on in a chip."
There are bunch of companies that offer system-level thermal analysis tools, but Chandra's company focuses solely on thermal problems during IC design.
The usual approach is to deal with IC thermal issues by adding a better fan to your system or package, Chandra said. "If you design to cool a chip, you are really designing to cool the average temperature of that chip," he said. "The temperature gradients, which are caused by the forcing functions of the power sources on the chip, remain. So you can apply a fan to bring down the average temperature of a chip from 100° to say 80° or 60° [C], but if there is a 30° gradient in the chip, that will be unaffected because the power sources still continue to bump up the power. By adding a fan, you've just giving it a way to take away the energy through the heat-conducting surfaces of the package."
However, he said, the heat's still there. And in fact it is speeding up subthreshold leakage, among other things. "At every process-geometry shrink, at 90-nm and especially 65-nm, subthreshold leakage grows exponentially," Chandra said, noting that a 10° temperature increase can cause a 30% impact in an IC's performance.
The company's initial offering, FireBolt, is a static thermal-analysis tool to measure thermal gradients in an IC substrate and head off thermal conditions that may adversely affect power and timing, or even lead to electromigration migration or latchup and device failure.
Users feed the tool the IC layout, power-analysis results, a process-technology file that outlines layers within the chip, their substrate, and all the devices on it, as well as the targeted IC package's boundary conditions.
"With this information, it is able to compute the temperature of each device and all interconnects at any of the X, Y, and Z coordinates within the chip," Chandra said.
This data is then written out to files. The company has a 3-D and 2-D viewer utility that allows users to actually navigate the contours of the chip and see the hot spots.
The tool can be used after synthesis, even before LEF/DEF (library/design exchange format) files are generated, by feeding FireBolt bounding boxes to locate hot spots in floorplanning. "If you give the tool a .lib library, it can tell you what the leakage current is," Chandra said, noting that with specific fab-leakage data, the tool can even locate "leakage runaways" within a design.
Designers can also use the tool once they have designed the clock tree and power bus. The tool can capture the temperature of clock-tree nets at different points of temperature gradients and feed it back into a delay calculator. "It can change the delays of the cells based on the actual temperature of the cells," Chandra said. "This gives you a more temperature-aware view of timing. If you are simulating the clock tree with Spice, we can put the temperature into the Spice."
Because the tool gives users an idea of where temperature is high on devices, it also gives them an idea of where subthreshold leakage will be particularly bad.
Engineers can also use the tool during detailed routing to analyze particular nets or substrates to direct designers to areas needing in-place optimizations. It can also be used in signoff to determine how temperature impacts voltage drop, leakage current, timing, signal integrity, and electromigration.
Fabs can also plug their proprietary electromigration rules into the thermal-analysis tool and use it to help customers better determine a reliability life cycle of their designs, Chandra said.
The engine behind the tool computes partial differential equations and thus doesn't need vectors to run. The tool can analyze a 6-million-gate design in a few hours, Chandra said. In one test run, the analysis came within 1°C of actual temperature in silicon, he added.
FireBolt starts at $150,000 for a one-year subscription.
The company is currently working on a second product, a transient-analysis tool that will dynamically trace thermal affects as an IC powers up and powers down. The tool will help engineers track transient temperature spikes that can cause catastrophic failures in a device. Chandra didn't give a release date for that tool.
Gradient's backers include former Cadence employees turned venture capitalists Lucio Lanza and Jim Hogan, as well as the company Cadence Design Systems.