Intel details PC graphics-aimed 'Larrabee'
Santa Clara, Calif-based chip giant Intel Corp will present a paper at the Siggraph 2008 conference being held next week in Los Angeles that details features and capabilities for its forthcoming multi-core “Larrabee” architecture which includes a new approach to the software rendering 3-D pipeline, a many-core programming model and performance analysis for several applications.
Intel said its first Larrabee-based product, not expected until next year or 2010, will target the PC graphics market and will be what the company said is the industry’s first many-core x86 Intel architecture. The company also expects Larrabee to spur efforts to create and optimize software for the dozens, hundreds and thousands of cores that will power computers in the future.
The chip giant reminded that it has a number of internal teams, projects and software-related efforts underway to speed the transition to multi-core, with its tera-scale research program garnering the single largest investment in its technology research and has partnered with more than 400 universities, DARPA and companies such as Microsoft and HP to move the industry in this direction.
Initial product implementations of the Larrabee architecture (an overview drawing of which is pictured below) will target discrete graphics applications, support DirectX and OpenGL, run existing games and programs, and support a range of highly parallel applications including scientific and engineering software that will benefit from the Larrabee native C/C++ programming model, Intel continued.
Further, the Larrabee architecture has a pipeline derived from the dual-issue Intel Pentium processor, which uses a short execution pipeline with a fully coherent cache structure in order to allow enhancements such as a wide vector processing unit (VPU), multi-threading, 64-bit extensions and pre-fetching, which should allow a massive increase in available computational power combined with the familiarity and ease of programming of the Intel architecture, the company explained.
The Larrabee architecture also includes a select few fixed-function logic blocks to support graphics and other applications, which are carefully chosen to balance strong performance per watt, yet contribute to the flexibility and programmability of the architecture.
Also, to make the writing of software programs simpler, Larrabee contains a coherent on-die second level cache, which is meant to allow efficient inter-processor communication and high-bandwidth local data to be access by CPU cores.
Supporting a variety of highly parallel applications, including those that use irregular data structures, the Larrabee native programming model allows development of graphics APIs, rapid innovation of new graphics algorithms, and true general purpose computation on the graphics processor with established PC software development tools.
Larrabee also contains task scheduling which is performed with software, rather than in fixed function logic so that rendering pipelines and other complex software systems can adjust resource scheduling based each workload's unique computing demand.
Intel said the Larrabee architecture also supports four execution threads per core with separate register sets per thread to allow the use of a simple efficient in-order pipeline, but retains many of the latency-hiding benefits of more complex out-of-order pipelines when running highly parallel applications. The architecture uses a 1024 bits-wide, bi-directional ring network (i.e., 512 bits in each direction) to allow agents to communicate with each other in low latency manner resulting in super fast communication between cores; and fully supports IEEE standards for single and double precision floating-point arithmetic, the support of which is a pre-requisite for many types of tasks including financial applications, Intel concluded.