Synopsys aims to speed design, verification tools with multi-core support
To allow IC design companies to easily maximize the throughput of multi-core compute infrastructures for reduced time-to-results (TTR), semiconductor design and manufacturing software tool company Synopsys Inc today announced a multi-core initiative to deploy advanced parallel, threaded and other optimized compute technologies across its Discovery Verification and Galaxy Design platforms, as well as its design for manufacturing (DFM) products.
Synopsys noted that this move builds on its multi-processor and network-distributed EDA tools and flows, including the VCS functional verification product with native testbench technology for compute farms and the Proteus lithography software tool. Additional multi-core-enabled products are set to be released throughout the year.
Further, the company reminded that the combination of increasing IC complexity and shrinking semiconductor features is driving exponential demand for design and manufacturing-related compute resources, which Synopsys believes it addresses by deploying advanced multi-core software and optimized information technology (IT) products that can deliver breakthrough productivity increases.
Synopsys plans to deliver this year its Galaxy Design Platform, Discovery Verification Platform and DFM toolset, including the Proteus OPC solution for mask synthesis; CATS mask data preparation; and Sentaurus TCAD tool suite for semiconductor process and device modeling.
Elwood Coslett, director of platform and design capability engineering at Intel reminded that the chip giant and Synopsys have a long history of engineering collaboration in the area of scalable compute infrastructure and advanced software engineering techniques. “Most recently, we have jointly worked to deploy and use the Intel Software Development Products (including the Intel Compilers, VTune Performance Analyzer, Intel Threading Analysis Tools, Intel Performance Libraries, and Intel Threading Building Blocks) to Synopsys' global software engineering community to enable rapid development of multi-core processor-based solutions.”
John Chilton, senior VP of marketing and business development at Synopsys explained in a statement, “We are now in an environment where the cost to house, power, and cool the IT infrastructure is greater than the capital acquisition cost. Simply throwing more hardware and data centers at the problem is neither economically viable nor environmentally sustainable.”
“In order to improve overall design time-to-results, EDA tools must increase throughput but also be deployed on optimized IT solutions specifically addressing the unique issues facing complex design-to-manufacturing processes. With the multi-core initiative, Synopsys is attacking these challenges on all fronts to accelerate design throughput for our customers,” he added.
For commentary on this move, please see this Practical Chip Design blog entry, "Synopsys tries to organize its efforts in EDA multiprocessing."