TSMC unveils 40-nm semiconductor manufacturing process
To support a performance-driven general purpose technology and power-efficient low power semiconductor manufacturing technology, Hsinchu, Taiwan-based semiconductor foundry Taiwan Semiconductor Manufacturing Co Ltd (TSMC) today announced its first 40-nm manufacturing process technology that includes a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models, and foundation IPs.
First wafers out are expected in Q2.
Highlights of TSMC’s 40-nm process technology include a 2.35 times raw gate density improvement over its 65-nm process technology; active power down-scaling of up to 15% over its 45 nm process technology; what the company believes is the smallest SRAM cell size and macro size in the industry; general purpose and low power versions for broad product applications; dozens of customers projects in the design pipeline today; and frequent and regular CyberShuttle with MPW prototyping running.
The company reminded that it has moved forward quickly to develop enhanced 40-nm low power (40LP) and 40-nm general purpose (40G) processes in order to deliver high performance with 40-nm density following successful tapeouts and customer announcements with its 45-nm process technology last year.
TSMC’s 45-nm node allowed double the gate density of its 65-nm manufacturing technology, while the 40-nm node contains manufacturing innovations that allow its LP and G processes to deliver a 2.35 raw gate density improvement of the 65 nm offering with the transition from 45- to 40-nm low power technology allowing a reduction of power scaling up to 15%.
“Our design flow can take designs started at 45 nm and target it toward the advantages of 40 nm," John Wei, senior director of advanced technology marketing at TSMC, explained in a statement. "A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives.”
Specifically, the 40LP technology was developed for leakage-sensitive applications such as wireless and portable devices, while the 40G variant targets performance applications including CPU, GPU, game console, networking and FPGA designs, and other high-performance consumer devices.
The company also pointed out that the 40-nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45-nm counterpart, making the SRAM cell size now the smallest in the industry at 0.242-square microns.
To match the breath of applications that can take advantage of the new node's size and performance combination, mixed signal and RF options accompany the 40G and 40LP processes along with embedded DRAM, TSMC said.
Also, TSMC’s 40-nm process leverages a combination of 193-nm immersion lithography and extreme low-k (ELK) material, with the logic family including a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications, while both the G and the LP processes supporting multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.
Finally, TSMC said its CyberShuttle prototyping service can be booked for 40-nm designs in April, June, August, October, and December with first wave 45- and 40-nm customers having already used above 200 blocks on completed multi-project wafer runs.
The 40G and LP processes will initially run in TSMC's 12 inch wafer Fab 12 and will be transferred to Fab 14 as demand ramps, the company concluded.
For analysis on this news, please see EDN Executive Editor Ron Wilson's Practical Chip Design blog entry, "Is it really a half-node? Anatomy of the 40-nm shrink at TSMC."