Open Verification Methodology ready for download from Cadence, Mentor
By Ann Steffora Mutschler, Senior Editor - January 9, 2008
Semiconductor design software companies Cadence Design Systems Inc and Mentor Graphics Corp today announced their jointly developed Open Verification Methodology (OVM) source code, documentation, and use examples are now ready for download, free of charge, from OVMWorld.org.
The companies first announced last August they would work together on the OVM.
The OVM is distributed under the standard open-source Apache 2.0 license from the OVM web site, which is the central point of access for the OVM source code, providing information about partners, events, seminars, training, how-to instructions and future plans, the companies noted.
Based on IEEE Std. 1800-2005 SystemVerilog standard, the OVM is the first open, language interoperable, SystemVerilog verification methodology, and consists of a methodology and accompanying library to allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces.
The OVM is also meant to allow intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.
As a joint development initiative between Mentor and Cadence, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers, the companies said.
The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable verification IP (VIP) in SystemVerilog and aims to reduce the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and shorten the time to create verification environments by integrating plug-and-play VIP and ensuring code portability and reuse.
Robert Hum, VP and general manager of Mentor’s verification and test business unit, noted that the OVM represents a major step forward in protecting customers' investment in verification flows and reusable verification IP and after extensive customer interaction; Mentor believes OVM will accelerate the move to SystemVerilog, and provide significant competitive advantage to design and verification teams around the world.
A production version of OVM is available now with additional functionality planned for later this year.
Both companies assert that they have collaborated to make sure that the OVM runs on their simulators and allows backwards compatibility with existing environments, Advanced Verification Methodology from Mentor Graphics, and Incisive Plan-to-Closure Methodology (Universal Reuse Methodology module) from Cadence.
For commentary on this story, see "Let the mayhem begin: Open Verification Methodology available for free download."