Intel Appoints New Fellows
In recognition of the technical achievements of six employees, Intel Corp. has appointed two senior fellows and four fellows.
The new senior fellows are Stephen Pawlowski and Ian Young. The new fellows are Boris Babayan, Timothy Deeter, Albert Fazio and Shiuh-Wuu Lee.
Pawlowski is the CTO and director of platform planning, architecture and technology in the enterprise platforms group (EPG). He joined Intel in 1982 and was appointed fellow in 2000. He currently leads EPG’s efforts to plan and design products that provide competitive advantage at both the component and platform levels. He led the design of the first multi-bus/single-board computer based on the Intel386 processor and has been a lead architect or designer for several key PC and server technologies including the system buses for Pentium III and Pentium 4-based PCs, the system architecture for servers based on Itanium processors and the 82450 GX and NX server chipsets. Pawlowski holds 52 patents in the area of system and microprocessor technologies.
Young, who joined Intel in 1983, is director of advanced circuits and technology integration in the technology and manufacturing group. Young was appointed fellow in 1995 and is responsible for defining and developing circuit designs and optimizing manufacturing process technology for high-performance microprocessors and communications products. He developed the original Phase Locked Loop-based clocking circuit for the 50 MHz Intel486 processor and subsequent generations of clocking circuits through the 3GHz Pentium 4 processor. More recently, he has lead development of communications technologies, including a CMOS 10Gbps multiplexer chip for optical networking and a CMOS RF radio transceiver chip for wireless LANs. He holds 36 patents.
Babayan is director of architecture in the software and solutions group and joined Intel this year. He leads worldwide compiler technology development efforts for Intel server products, technologies that enable applications to run on multiple computer architectures without recompiling, as well as Intel security technologies. He has led the teams that build supercomputers for the former Soviet Union and holds 11 U.S. and five Russian patents.
Deeter joined Intel in 1981 and is director of design rules and tapeout technology in the logic technology development group, part of the technology and manufacturing group. He is in charge of developing microprocessor physical design parameters. He has been involved in specifying design parameters and validation methodologies for every Intel microprocessor technology since 1985. He holds five patents.
Fazio is director of memory technology development in the technology and manufacturing group and joined Intel in 1982. He is responsible for developing flash memory and multi-level cell memory technologies as well as novel memory technology ideas. He was responsible for the development of the Intel StrataFlash memory and has been involved in a number of other memory development programs at Intel including SRAM, EPROM and NVRAM. He holds 24 patents.
Finally, Lee is director of advanced circuit simulation computer-aided design (CAD) in the technology and manufacturing group, and joined Intel in 1987. He currently leads R&D of CAD technologies used to design Intel products. Before joining Intel, Lee served as a member of the technical staff at AT&T Bell Labs. He has initiated development of a number of leading CAD tools used to address difficult chip design challenges. He has authored 39 technical articles and conference presentations.