The next transistor: planar, fins, and SOI at 22 nm

The race is on to redefine the transistor. Process developers working on 22-/20-nm logic processes appear to be scrambling to introduce new kinds of transistors for this node. Intel has made a huge fanfare over their tri-gate device. Many researchers are pushing finFETs. A powerful group of mainly European organizations, including ARM and US-based Globalfoundries, is serious about fully-depleted SOI (fdSOI.) And recently, start-up Suvolta and Fujitsu described yet another alternative.

All this might appear fascinating for device designers, and irrelevant to chip designers. But decisions on transistor design will have profound downstream impacts-from the craft of cell design to the work of physical-design teams, and even to the logic designer's struggles with power and timing closure.


Why are process engineers so determined to upset the apple cart? The short answer is short-channel effects. Pursuit of Moore's Law has continually shrunk the channel length of the MOSFET. This contraction improves transistor density and, other factor fixed, switching speed. The problem is that shortening the channel plays havoc with those other factors-about a dozen different havocs, actually, that get lumped under the label of short-channel effect. Most of these we can summarize by a generalization: as the drain gets closer to the source, it gets harder and harder for the gate to pinch off the channel current (figure 1, below). The result is sub-threshold leakage current.

This battle against leakage current has been going on since at least the 90-nm node. The point of the whole high-k/metal-gate (HKMG) transition was to give the gate more control over the channel current without letting gate leakage get out of control. But by the 22-nm node, many are arguing, the planar MOSFET will have lost that war. There will be no way to deliver adequate leakage control at adequate performance. "With HKMG we addressed gate leakage," one expert said. "Now we have to address channel leakage."
 

Planar one more time?

Not everyone agrees that the planar MOSFET is history. Principal among the dissenters is TSMC, which stated in February that it would use planar transistors in its 20-nm foundry process. There are strong arguments for this position, also held-with one major caveat-by Globalfoundries. Designers are familiar with short-channel planar MSOFETs, for all their shortcomings. This should make rescaling of cell libraries and hard IP blocks relatively straightforward. Leakage and threshold variations may be worse than at 28 nm, but the design community has tools, including aggressive power management, variation-tolerant circuits, and statistical timing analysis, to cope with these problems. And when all the issues are on the table, a foundry must do what its lead customers-FPGA vendors, networking IC giants, and to some extent ARM-ask of it.

Still, there is much skepticism. "TSMC stated that they would use a replacement-metal-gate planar process at 20 nm," observed Novellus Vice President Girish Dixit, "but that determination may have changed. HKMG can control leakage, but a planar transistor will still have inferior I-on/I-off characteristics." If TSMC's early adopters find themselves at a competitive disadvantage because of the planar transistor, they may force the giant into a finFET half-node. The confrontation would most likely arise in the mobile market, where ARM's fabless silicon partners will face competition from Intel's Atom processor, newly rejuvenated by that company's 22-nm tri-gate process.

 

The rise of the fin

The next-transistor debate matriculated from a decade in the cloistered but technically accurate halls of process engineering conferences to the public forum with Intel's May announcement of their 22-nm so-called tri-gate process. The roll-out, probably intended to counter ARM's growing momentum in the mobile space rather than to advance the discussion in circuit design, significantly reduced the signal-to-noise level about new transistor technology.

Intel's tri-gate device is a finFET, pure and simple. Industry experts dismiss Intel's attempts to claim a significant difference. As such, it is one instance of a decade-old, industry-wide attack on short-channel effect-an effort that began at industry consortium IMEC at about the same time as it did at Intel. "Everyone in the industry has been developing finFET technology," one process expert said. "The difference is in what they have chosen to announce."

All finFET programs-indeed, all the approaches to next-transistors-rest on a single concept: the fully-depleted channel. Loosely, the concept is to give the gate so much control over the electric field in the channel that the gate can deplete the channel of carriers entirely. This of course eliminates the dominant conduction mechanism in the channel, and in effect turns the transistor off.

But how to do that? In a planar device, the depth of the channel and effects from the junction formed between the drain and the silicon around it alter the electric field in the channel and interfere with depletion. Somehow you have to make the channel thin enough and far enough from the drain junction to permit the gate to fully deplete the conduction region.

The finFET solution is to stand the channel on its edge, above your choice of either the silicon surface or an insulating oxide layer, and to drape the HKMG gate stack over the resulting fin like a wet blanket. This fin-shaped channel is very thin (figure 2, right) and working from three sides, the gate can successfully create a depletion region that blocks the channel entirely.

The finFET gives circuit designers a V-I curve they've only been able to dream about since 130 nm. But it also brings issues. One is simply building the devices. "Making the fins, and preserving them through subsequent processing steps, are hard tasks," warned Applied Materials Silicon Systems Group Vice President and CTO Klaus Schuegraf. "You must etch over the edges of tall structures, uniformly dope complex 3D surfaces, and lay down all the different films in the gate stack so that they conform exactly to the surface of the fin. These requirements bring about many changes in materials, and some changes in equipment. The number of mask layers won't change much, but the number of processing steps will certainly go up."


Continue reading: Fins and the rest of us