Synopsys debuts DesignWare STAR ECC IP
Robert Ruiz, Synopsys senior product marketing manager, noted that test impacts design and design impacts test, thereby contributing to the need to expand synthesis-based test technology to increase designer productivity.
Ruiz specifically noted that scan flops and chains, memory BIST, text-vector compression circuitry, and boundary-scan circuitry all affect design characteristic such as flop count, number of pins, and clocking schemes, leading to design goals (meeting timing, power, area, and floor-plan constraints) can conflict with test goals (meeting quality and test-cost requirements). The conflicts in turn can lead to unproductive design iterations that, Ruiz said, Synopsys's synthesis-based test technology can help avoid. The applicable tools, he said, include scan test (DFTMAX compression and TetraMAX ATPG), memory test and repair (DesignWare STAR memory system), high-speed I/O BIST (DesignWare IP), and yield analysis (Yield Explorer and TetraMAX ATPG).
Chief architect Yervant Zorian focused on the memory self-test and repair technology. He noted that advanced semiconductor fabrication has resulted in increased defect profiles, with transient errors induced by temporary environmental conditions, power-supply interconnect noise, electromagnetic interference, and electrostatic discharge. Particularly troublesome, he said, are telluric rays produced directly inside ICs and secondary cosmic rays in the earth's atmosphere.
The STAR ECC technology, Zorian said, provides an automated design implementation and test diagnostic flow that enables SoC designers to address multiple transient errors in SoC designs for automotive, aerospace, high-performance-computing, and other mission-critical applications. He said that designers can select their desired level of fault tolerance with respect to multibit upsets and random bit errors.