CEVA unveils x1643 DSP core, targets SoC migration path

-September 07, 2010

Targeting one of the most lucrative segments of the DSP migration market, Ceva Inc. announced its fourth-generation CEVA-X1643 DSP core with support for TI C6x code.

The CEVA-X1643 is a 1GHz engine with added memory- and power-management features targeted at the wireless handsets, wireless infrastructure and personal media player (PMP) markets. The device is intended to provide designers with an easy migration path from TI C6x (see chart below) implementations into SoC/ASSP designs where they can wring out some cost and optimize performance and power-management features.

Key features:
  • 1GHz performance at 40nm design rules
  • Integrated Power Scaling Unit (PSU)
  • 0.3mm2 at 40nm
  • Fully cached memory architecture
  • Standard 64/128-bit AXI bus support
  • Compatible with TI C-level source code

The device is the latest in the eight-year-old Ceva-X line (x1620, 1622, 1641—see chart below), which is based on an eight-way very long-world instruction set (VLIW) architecture and single-instruction multiple data (SIMD) capabilities.

The major change to the Ceva-X approach is the addition of the power scaling unit—originally conceived for the company’s CEVA-XC low-power DSP core—to allow designers to better manage power depending on application demands. Simply put, it allows portions of the logic to be toggled off when they’re not needed, saving on both dynamic and leakage power dissipation.

The PSU supports multiple operational modes ranging from full operation, debug bypass, memory retention, to complete power shut-off.

    Eran Briman, vice president of marketing at CEVA, claims the benefits on dynamic power leakage of the power scaling unit can be anywhere from a few percent to up to 80 percent, depending on application. In addition, the core itself supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches.





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    CEVA-X1643-TI C6x Comparison

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    CEVA-X1643 TI C6x

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    DSP type 8-way VLIW 8-way VLIW

    .


    Max Speed > 1GHz 1.2 GHz (TCI6487)

    .


    Software nature C based + intrinsic functions C based + intrinsic functions

    .


    Memory utilization Load-store machine, 32-bit addressing space Load-store machine, 32-bit addressing space

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    Cache support Full: data and program Full: data and program

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    Sample MIPS (H264-BP 30FPS, D1 res., 4 Mpbs) Encoder: 220 MHz
    Decoder: 140MHz
    Encoder: 674 MHz
    Decoder: 336MHz

    The need for speed
    CEVA also crafted the 1643 with an eye toward the bulging performance demands of next-generation multimedia devices. So rather than continue to rely on the AHB bus, which is supported in the 1620, 1622 and 1641), the 1643 uses the AXI bus.

    “AHB was sufficient a few years ago, but with i/o data rates going up, AHB wasn’t cutting it,” Briman said.

    The 1643 is supported by CEVA-Toolbox, a software development, debug, and optimization environment, which allows designers—among other things—to develop software purely in C-Level.
    • In a January 2010 webinar, CEVA executives described ways to optimize software development flow.
    • Below, in the embedded video, CEVA explains the x1643 device.


    Pricing
    : Dependent on application, market considerations.

    Availability: Now Some 25 companies have bought licenses for the CEVA-X family, the company said.

    Earlier this year, the Chinese firm Rockchip came to market with a system for 720p high definition, multi-standard video using the CEVA-MM2000, which is based on the x1622.



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