Custom core takes on standard DSPs
The combination of a compiler-friendly 8-way VLIW and SIMD architecture, an advanced data cache architecture and memory management is claimed to enable licensees to efficiently migrate legacy code from off-the-shelf DSPs and ensures similar DSP performance levels at a significantly lower price point.
The CEVA-X1643 DSP features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. With a well-balanced pipeline, the CEVA-X1643 can run at over 1GHz in chips implemented at the 40nm technology node.
The IP is equipped with an Advanced eXtensible Interface (AXI) based memory sub-system, supporting configurable AXI bus width, parallel read and write transactions, read after write transactions and other advanced capabilities. It is claimed that the use of de-facto industry standard system buses together with a fully cached CEVA-X processor enables high performance, shorter design cycle and easy integration into the target SoC.
The DSP core also includes a Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches. The PSU supports multiple operational modes ranging from full operation, debug bypass, memory retention, to complete power shut-off (PSO). Furthermore, the AXI full duplex busses buses offer low-power features, such as the ability to shut down when no data traffic is present.
For more information visit: www.ceva-dsp.com
Courtesy of EE Times Europe.