Cadence unveils parallel circuit simulator for the verification of complex analog and mixed-signal IC designs
Cadence Design Systems has announced the availability of the Cadence Virtuoso Accelerated Parallel Simulator (APS), its next-generation circuit simulator, which constitutes a key part of the Cadence Multi-Mode Simulation solution (MMSIM) 7.1 release.
According to Cadence senior architect John Pierce, the new simulator helps customers contend with shrinking product windows—which have shrunk from two years down to 12 or as few as six months—and the ever longer simulation times demanded by increasingly complex designs using traditional simulators. APS, he said, reduces mixed-signal simulation turnaround time from days or weeks to a few hours.
According to Nebabie Kebebew, a senior product manager at Cadence, the new simulator provides significant single-thread and scalable multithread performance boosts while maintaining accuracy equivalent to that of the Cadence Virtuoso Spectre circuit simulator. APS, she added, also supports an identical use model to Spectre.
Kebebew said that more than 20 beta customers have tested the new simulator on more than 200 designs for devices including PLLs, DACs, ADCs, memory, power-management circuits, and high-speed I/O circuits. One customer, she said, experienced a 60× performance speedup for the simulation of a 65-nm PLL design running on an eight-core system. Another customer, she said, experienced 58× performance improvement for the post-layout simulation of a DC/DC converter, reducing runtime from 20 hours and 16 minutes to 21 minutes.
The new simulator consists of a combination of Cadence simulation technologies and a parallel circuit solver, along with a newly architected engine that harnesses the power of multiprocessing computing platforms. The Virtuoso Accelerated Parallel Simulator improves convergence and capacity for designs with hundreds of thousands of transistors, reducing design and verification time in most cases from weeks to hours.
"We are pleased to find a next-generation simulator on the market that can keep pace with our performance requirements for top-level simulation of custom digital and analog designs, such as a DC/DC converter," said Helmut Schweiss, director of new business start-ups at ON Semiconductor, in a press release. "The Virtuoso Accelerated Parallel Simulator delivered a 20.6 times performance boost over traditional Spice simulators, which enabled us to verify and detect multiple design issues and meet our critical tapeout deadline. This would not have been possible otherwise and eliminated unwanted surprises during our silicon verification."
"Productivity boost in our verification flow is a critical requirement and we are very encouraged to see a next-generation Spice simulator on the market that can handle large, complex designs we are creating," said Raed Moughabghab, director of the mixed-signal design group at Entropic Communications, in a press release. "We validated Virtuoso Accelerated Parallel Simulator on our existing design and realized a 2.5 times performance over Spectre with turbo, and 12.5 times performance over Spectre with a four-core compute platform, and plan to use it on the next design project."
The new simulator is compatible with existing Cadence simulation technologies, enabling customers to preserve investments made with the Virtuoso custom IC platform. "Over the past eight months, we have introduced several compelling new simulation technologies," said Zhihong Liu, corporate vice president of research and development for circuit simulation and physical verification products at Cadence. "In April we brought a significant performance boost to the Virtuoso Spectre Circuit Simulator with our 'turbo' capability, and two months later we brought the turbo power to our RF simulation technology. The Virtuoso Accelerated Parallel Simulator is a significant addition to our Virtuoso Multi-Mode Simulation technology, serving as the simulation platform for a cost-effective, scalable and reliable solution for teams whose large, complex analog designs pose some of today's greatest design challenges and verification bottleneck."