Tanner EDA announces router, layout-device generator
At the Design Automation Conference, which took place in July in San Francisco, Tanner EDA introduced the SDL (schematic-driven-layout) interactive autorouter and the DevGen layout-device generator. The company also announced that it is shipping Version 14.10 of its Tanner Tools Pro and HiPer Silicon products, which serve full-custom analog and MEMS (microelectromechanical-system) design.
Tanner EDA’s SDL software integrates the new SDL Router automatic-routing engine. It speeds layout by automatically routing noncritical nets and allowing designers to focus on routes that require expensive handcrafting to achieve performance or to address analog-sensitive nets or parts of nets. A layout engineer interactively controls the router, which natively employs user-created routing geometry; it runs on all or a specified subset of nodes on each pass. Users can manually route part of a net and have the router automatically finish routing the net. Users can highlight and rip up nodes, manage the manual and automatic routing status, and implement engineering change orders.
Using DevGen along with SDL allows analog-layout designers to become more productive by automating much of the tedious task of laying out devices. DevGen provides parameterized layout generators that are configurable for any process. By using the DevGen wizard and answering a few questions about the layers involved and the DRCs (design-rule checks), designers can create parameterized cells of common devices without writing code. DevGen includes layout generators for capacitors, resistors, inductors, MOSFETs, and diodes.
SDL Router and DevGen maintain close synchronization between the schematic and the layout. SDL automates instancing of cells and parameterized devices and placement quality by displaying real-time node fly lines. It also helps avoid routing congestion and tracks an engineer’s progress to help manage workflow.
Besides the new SDL Router and DevGen, Version 14.10 of Tanner Tools Pro and HiPer Silicon include improved Verilog-A integration, which reduces analog-simulation runtime when simulations include digital blocks, and HiPer Verify, which natively runs Calibre, Dracula, and Assura foundry files without conversion or modification. The tools perform SOA (safe-operating-area) checks in T-Spice, so models stay valid and circuits operate correctly. Interactive DRC displays violations in real time during layout editing. The software displays the spacing distance in real time while the designer edits the layout and can prevent editing from getting closer than the minimum distance. Prices for the packages start at $25,000.