Speedy Spice-accurate simulator targets analog, RF
By Michael Santarini, Senior Editor - July 24, 2006
Most analog and RF engineers rely on Spice simulators for accurate circuit analysis, but Spice simulation is painfully slow. Over the years, EDA vendors have attempted to speed Spice simulation for engineers by introducing fast-Spice simulators. Although the tools speed simulation, they compromise accuracy. Officials at Berkeley Design Automation believe they have solved this problem with two tools that it claims are Spice accurate and five to 10 times faster than competing tools.
According to EDA veteran Paul Estrada, Berkeley's chief technology officer, the company merged its patented, stochastic, nonlinear simulation engine from its PLL-Analyzer tool with a fast sparse-matrix solver, a global-convergence solver, adaptive time-stepping technology, latency-exploitation algorithms, a fast stiff-DAE (differential-algebraic-equation) solver, a unified time/frequency engine, and a device-sensitivity analyzer to create the Analog FastSpice time-delay, or transient-analysis, simulator and the RF FastSpice periodic-convergence-analysis add-on for Analog FastSpice.
Tom Ferry, the company's vice president of marketing, says the tools target simulation of large, critical blocks, giving analog and RF engineers a reliable and accurate fast Spice-class tool. He notes that most fast-Spice tools use a divide-and-conquer approach: They piece a design into mini blocks, and users then tune the blocks' performance before they simulate their circuits. In some cases, tuning blocks can take more time than running a pure-Spice simulation. The Berkeley tools, in contrast, do not break down circuits into mini blocks and require no tuning, says Ferry. Instead, users input their Spice netlist into the tool and then simply run the simulation.
"The result of this technology is an order of magnitude improvement in verification bandwidth," says Ferry. "If you are designing an RF CMOS or a 65-nm SOC [system on chip] with 32 SERDES [serializer/deserializer] ports on it, having this much more bandwidth is amazing." Beta customers have run the Analog FastSpice tool on several designs. A SERDES-circuit design comprising 4200 devices in a 0.13-micron implementation took 5.4 days to run in pure Spice but only 7.2 hours with Berkeley's tool, Estrada claims. The company ran benchmark tests of its tool versus pure Spice on several 802.11 circuits targeting 0.18-micron technology. A 107,264-device IC took 1.2 hours to run in pure Spice and nine minutes to run in Analog FastSpice. At the other end of the spectrum, a complex circuit with 25,522 devices took 6.25 days to run in pure Spice but only 15 hours with Berkeley's tool, Estrada claims.
In benchmarking the RF FastSpice against the most popular commercial simulator, the commercial simulator couldn't finish most designs, the pure-Spice tool was unable to finish four of the seven benchmarks, but RF FastSpice completed them all. The simulator completed a digital-TV circuit with 8590 devices in 28 minutes and another TV circuit with 6548 devices in 10 minutes. The pure-Spice tool finished one wireless circuit in 45 minutes, a second wireless in 100 minutes, and a networking circuit in 40 minutes, compared with 4.5 minutes, 100 seconds, and four minutes, respectively, for the RF FastSpice.
The RF version of FastSpice supports complex blocks, such as a voltage-controlled oscillator, a crystal oscillator, a low-noise amplifier with mixer a circuit, and a power-amplifier circuit. The company tailored the tools to plug into the Cadence Virtuoso ADE (analog-design-environment) flow. The tools are compatible with HSpice and Spectre netlists, and they run with traditional models, such as BSIM (Berkeley short-channel IGFET model) 3 and 4, Verilog-A, and s-parameter. Analog FastSpice costs $95,000 for a one-year subscription, and RF FastSpice costs $40,000 for a one-year subscription.