Resolve A/MS verification challenges from a single platform

HiPer Simulation A/MS combines Tanner’s EDA’s analog design capture and simulation tool with Aldec’s mixed language digital simulator. Analog and digital designers can seamlessly resolve A/MS verification problems from a single integrated platform.

Available on Windows and Linux, the product includes Tanner EDA’s design entry and simulation tool suite for analog design, S-Edit for schematic capture, T-Spice for circuit simulation with Verilog-A modeling, W-Edit for waveform probing, and Riviera-PRO (TE), the Tanner Edition of mixed VHDL and Verilog simulation from Aldec.

For more information contact Tanner EDA