The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X
The Suite provides a highly integrated design environment (IDE) with a new generation of system-to-IC level tools built on the backbone of a shared scalable data model and a common debug environment.
To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance. To address implementation bottlenecks, Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a 'cost' function of multiple variables such as timing, wire length and routing congestion.
The Vivado Design Suite version 2012.1 is available as part of an early access program. Customers should contact their local Xilinx representative. To learn more, visit www.xilinx.com/design-tools.