Multi-core SoCs combine ARM Cortex-A15 and C66x DSPs

-November 13, 2012

TI has extended its KeyStone line of multicore SoCs with a new family of devices that combine ARM Cortex-A15 processors with TI's own C66x DSP cores and dedicated support for security processing, packet processing, and Ethernet switching.

Figure. TI's new SoCs combine different combinations of ARM Cortex A15 cores, TI C66x DSP cores, and memory stores. (Courtesy of Texas Instruments)

Implemented in 28 nm technology, the family offers multicore devices ranging from 2 to 12 cores at speeds from 800 MHz to 1.4 GHz while operating at power levels ranging from 6 W to 13 W. The new family includes core and memory configurations targeted for high-end networking applications, enterprise and industrial applications, and special-purpose server applications designed to offload compute-intensive tasks from conventional servers.

KeyStone Multicore SoC




1 Cortex-A15 processor

1 C66x DSP

Enterprise video, IP cameras (IPNC), traffic systems (ITS), video analytics, industrial imaging, voice gateways, portable medical devices


4 Cortex-A15 processors

1 C66x DSP


2 Cortex-A15 processors

4 C66x DSPs

High performance computing, media processing, video conferencing, off-line image processing & analytics, video recorders (DVR/NVR), gaming, virtual desktop infrastructure, medical imaging


4 Cortex-A15 processors

8 C66x DSPs


2 Cortex-A15 processors

Cloud infrastructure, routers, switches, networking control plane, wireless transport, radio network control, industrial sensor control

 AM5K2E04 4 Cortex-A15 processors

The new devices integrate the ARM and TI cores with several memory stores, including 4 MB of shared memory for the ARM cores, 1 MB for each DSP core, and additional memory shared across all cores through the KeyStone's MSMC (Multicore Shared Memory Controller), which also provides access to additional external memory as needed. At the same time, KeyStone's TeraNet serves as a high-speed interconnect fabric linking device resources.

Most significant, the KeyStone architecture features a 256-bit data path and twice the interface clock rate that enable KeyStone devices to perform at twice the interconnect bandwidth of typical ARM-based designs. Along with the KeyStone MultiCore Navigator, which assigns tasks to available on-chip resources, the architecture is able to achieve maximum utilization of cores in high-performance applications.

The new SoCs are supported by the TI Code Composer for C/C++ and assembly language development as well as Open MP and Open CL for multicore development. EVMs (evaluation modules) will be available in 2Q13 for under $1000 each.

The 66AK2Hx SoCs are currently available for sampling, with broader device availability in 1Q13. AM5K2Ex and 66AK2Ex samples and EVMs will be available in the second half of 2013. Pricing for these devices will start at $49 for 1,000-unit quantities.

For more information, visit TI or follow the links below for datasheets:

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