Software toolkit unifies debugging across ARM and FPGA domains in Altera SoCs
Altera SoC devices combine a dual-core ARM Cortex-A9 processor with FPGA logic on a single device, enabling developers to create custom field-programmable SoC variants by implementing user-defined peripherals and hardware accelerators in the FPGA fabric. The DS-5 toolkit dynamically adapts to unique FPGA configurations within the SoC to unify all software debugging information from the CPU and FPGA domains with the standard DS-5 user interface.
Key features of the ARM DS-5 Altera Edition toolkit include:
- Software debug view adapts to include the peripheral devices programmed by the developer into the FPGA fabric, providing a seamless view of both the hard and soft peripheral register memory map of the entire SoC.
- The DS-5 Debugger simultaneously displays debug/trace data for the Cortex-A9 processor cores and CoreSight-compliant custom logic cores implemented in the FPGA fabric.
- Altera USB-Blaster JTAG debug cable supports both the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device.
- Allows non-intrusive capture and visualization of signal events in the FPGA fabric that can be time-correlated with software events and processor instruction trace.
- Supports advanced, signal-level hardware cross-triggering between the CPU and FPGA logic domains, which enables cross-domain hardware/software co-debugging.
- Includes the DS-5 Streamline performance analyzer, which correlates software thread and event information with hardware counters from both the SoC and FPGA, enabling the identification and correction of system-level bottlenecks.
More information about the Altera SoC EDS, visit www.altera.com/soc-eds.
More information about the ARM DS-5 Altera Edition toolkit, visit www.altera.com/ds-5-ae.