Imec, Cadence develop 3-D memory-on-logic DFT tool
The test methodology, which is based on the Cadence Encounter Test platform, was verified on an industrial test chip containing a logic die and a JEDEC-compliant Wide I/O mobile DRAM.
Memory-on-logic 3-D ICs offer many benefits for low-power mobile applications. The Wide I/O standard allows up to four DRAM dies, or ranks, to be placed on top of a logic die or on an interposer substrate. Wide I/O also includes boundary scan features to facilitate interconnect testing.
The Imec/Cadence solution leverages a DFT architecture and corresponding ATPG (automatic test pattern generation) approach, including support for post-bond testing of the interconnects between the logic die and the DRAM stacked on top of it. All 3-D DFT logic in the logic die was automatically inserted with a Cadence Encounter RTL compiler, while the interconnect test patterns were generated with an Encounter Test ATPG.
Cadence Design Systems, www.cadence.com
Find datasheets on products at Datasheets.com, searchable by category, part #, description, manufacturer, and more.