Timing signoff tool boosts performance, accuracy for faster closure
Faced with a combination of shrinking geometries and increasing design complexity, engineers must contend with a rapidly growing number of timing views and increased processing requirements for analysis (Figure 1). As a result, time spent in timing closure for 20nm designs accounts for up to 40% of the design flow, according to Cadence.
Figure 1. Timing closure accounts for an increasing share of project schedules with the increase in number of timing views with advanced processes (left) and associated increase in runtime for associated with a growing number of views (right). (Courtesy of Cadence Design Systems)
With Tempus, Cadence is tackling the timing closure bottleneck by addressing what it considers the three key issues facing timing closure:
- Performance, by supporting massively parallel computation based on relatively low-cost processing nodes managed by industry standard workload platforms such as LSF (Load Sharing Facility). Using a proprietary algorithm, Tempus distributes timing analysis across hundreds of CPUs in a manner that is transparent to the user.
- Accuracy, by combining advanced foundry-validated process models with a new path-based analysis algorithm required for parallelism. As a result, Tempus is able to provide more accurate timing analysis with results that are 3% less pessimistic - a margin that can be used to complete signoff sooner or to improve power performance.
- Closure - by bringing a physical view of the design into timing analysis, allowing engineers to not only identify problems but also fix them in the same environment (Figure 2). In the process, Tempus ensures that each fix is correct across all views. This enhanced closure capability enables a "physically-aware" ECO methodology that can result in up to a 10x productivity improvement in design closure, according to Cadence.
Figure 2. Cadence Tempus melds physical design views with a multimode, multicorner capability and physically-aware optimization to support a physically-aware ECO flow capable of significantly speeding timing closure. (Courtesy of Cadence Design Systems)
Cadence is targeting Q3 2013 for general availability of the Tempus Timing Signoff Solution. Users will be able to extend the master license across large numbers of CPUs through additional licensing packs.
For more information, visit Cadence Design Systems.