Design Con 2015

28-Gbps multiplexer offers multitap de-emphasis

-August 15, 2013

Agilent Technologies’ M8061A 28.4-Gbps multiplexer furnishes optional de-emphasis with up to eight taps for characterizing receivers for next-generation servers, storage systems, and data-center networks. The two-slot AXIe module, which extends the pattern-generator bit rate of the company’s J-BERT N4903B bit-error-ratio tester, allows engineers to emulate transmitter de-emphasis and channels, as well as compensate for losses in the test setup.

The 2:1 multiplexer is transparent to jitter from J-BERT and provides additional clock/2 jitter-injection capabilities. Built-in superposition of level interference eliminates the need for external power splitters that can cause level and signal degradation. The M8061A’s DC-coupled output allows engineers to generate unbalanced bit patterns without level drift, and it can be switched to an electrical idle state for computer bus receiver tests, such as those required for PCI Express.

When the M8061A is added to an existing J-BERT test setup, the equipment can be used to test multiple-gigabit applications, such as PCIe, USB, SATA, QPI, Hypertransport, Thunderbolt, DisplayPort, SD UHS-II, MIPI M-PHY, 10-Gb and 100-Gb Ethernet, SFP+, and CFP2 interfaces.

Prices for the M8061A multiplexer with optional de-emphasis start at $45,750.

M8061A multiplexer datasheet

Agilent Technologies, www.agilent.com

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