Pushing emulation beyond functional tests
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Typically for power measurement, chip designers only run simulations of functional tests at the block or subsystem level, generating switching activity in the form of Switching Activity Interchange Format (SAIF), Fast Signal Database (FSDB) or Value Change Dump (VCD) for a limited number ranging from tens to thousands of cycles. Power analysis tools do the rest and the power numbers are then extrapolated to get a power number for the full SoC.
But this approach was no longer enough for fabless chip vendor Qualcomm whose feedback to Mentor Graphics last year initiated new software developments around the company's Veloce2 emulation platform.
The EDA company who claims a double digit growth for its Emulation Division has replaced its FSDB-based power analysis flow, deemed unpractical for long emulation runs, with a Dynamic Read Waveform API integration to power analysis tools.
This Dynamic Read Waveform API approach captures the information from the power switching activity plot and transfers that data to power analysis tools, enabling accurate power calculation at the system level, better power exploration at RTL for power budgeting and trade-offs as well as more accurate power analysis and sign-off at the gate level.
With this approach, Mentor says its customers can now measure power in a targeted application environment while running actual software applications, from booting an OS to running hundreds of millions of cycles of real applications.
This means chip companies can now identify power issues that would only occur in real application environments and that may not be spotted during benchmarking tests.
The new flow is also said to offer a significant boost in the emulator's runtime performance, up to 4.5X according to partners who had early access to the new tool.
"It took us about a year to develop the Veloce Power Application software", told us Eric Selosse, Vice President & General Manager of Mentor Graphics' Emulation Division, "and I believe that for differentiation, the trend in emulation will be to have more and more software applications tied to the hardware" he added, referring to Mentor’s VirtuaLAB launched in 2013.
"This new application would have been difficult to develop prior to the launch of Veloce OS3 in April last year, and it will certainly take some time for our competitors to catch up", noted Selosse, "but I wouldn’t be surprised if Cadence announced something similar soon as this is what generally the industry has been asking for".
According to Selosse, emulators have become real competitiveness tools for large chip designers, and despite the shrinking number of very large chip designs, emulators are increasingly in demand because they are the only way to truly ensure full design functionality.
"Contrarily to many analysts’ predictions, the cloud is not threatening the emulation market, because even large server farms fall short of the performance of a dedicated machine. Today’s emulators are about a thousand time more performant than typical servers, for some designs this can mean 2 to 3 days of runtime versus several months on a cloud-based server farm" commented Selosse.
"What's more, although everyone is talking about the cloud, most chip designers are too concerned about IP security to let anything go to the cloud. They'll share their emulators internally, over private networks or implement their own private cloud of emulators".
In view of these new developments, something far out on the roadmap would be to close the loop and directly feedback the emulation’s power analysis into a RTL power optimization tool at chip design level. For now, all the early trade-off and exploration would have to be done manually, going back and forth between the tools, but customers are asking for further integration and this is something Mentor is also looking at.
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