64-layer flash IC enables 1-Tbyte chips

-March 05, 2017

Toshiba has added a 512-Gbit (64-Gbyte), 64-layer flash memory device that employs 3-bit-per-cell TLC (triple-level cell) technology to its BiCS Flash product line. This technology will allow the development of 1-terabyte memory chips for use in enterprise and consumer solid-state drives.

BiCS (Bit Cost Scaling) Flash is a three-dimensional flash memory stacked-cell structure suitable for applications requiring high capacity and performance. The 512-Gbit BiCS Flash device is based on a third-generation 64-layer stacking process that achieves a 65% larger capacity-per-unit chip size than the company’s 48-layer, 256-Gbit (32-Gbyte) device. The resultant increase in memory capacity per silicon wafer also leads to a reduction of cost-per-bit.

In addition to the new 512-Gbit device, which is now sampling and scheduled for mass production in the second half of 2017, the BiCS Flash portfolio includes a 64-layer, 256-Gbit offering that is currently in mass production. The next milestone on Toshiba’s BiCS Flash development roadmap will feature the industry’s largest capacity—a 1-terabyte product with a 16-die stacked architecture in a single package. Sample shipments of the 1-Tbyte device are planned to commence in April of this year.

Toshiba America Electronic Components

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