Aldec Europe: AVMS EI-02 - Rapid ASIC emulation in FPGA with HES

We will explain how an ASIC design can be setup for emulation at 1 to 5 MHz using Design Verification Manager (DVM) – a part of ALDEC’s HES product line. Aldec developed several revolutionary algorithms of FPGA partitioning and cross-chips synchronization that guarantees your ASIC up and running in FPGAs in just a few hours.

Location: Online: Thursday 9/18/2008, 3:00 PM (Central European Summer Time (CEST))
Date: 9/18/2008 - 9/18/2008
Organizer: Aldec, Inc.

We will explain how an ASIC design can be setup for emulation at 1 to 5 MHz using Design Verification Manager (DVM) – a part of ALDEC’s HES product line. Aldec developed several revolutionary algorithms of FPGA partitioning and cross-chips synchronization that guarantees your ASIC up and running in FPGAs in just a few hours.

Presenter: Presenter: Aldec, Inc. Jaroslaw Kaczynski, Technical Marketing Engineer

Agenda:

• Cross-FPGA design partitioning with signal multiplexing
• External stimulus synchronization
• Driving the emulation
• Integration with prototyping boards

Event Link:http://www.aldec.com/Products/Evaluation.aspx?productevaluationid=2bb2a8b5-bd1e-4a69-9af8-4009c1dde849