SystemVerilog Assertions Language and Methodology Overview Seminar

System Verilog Assertions (SVA) is a powerful subset of the IEEE 1800 System Verilog standard. Its hardware oriented concurrent semantics significantly reduce time to develop complex multi-clock domain checkers. Assertions also provide white box observability resulting in a drastic reduction of debug time, further reducing time to production. SVA allows a clean separation of design and verification logic and parameterization of properties resulting in a modular and reusable methodology

Location: Sunnyvale, CA
Date: 12/16/2008 - 12/16/2008
Organizer: Aldec

Agenda:
SVA Methodology
• What's an assertion? What are the advantages of SVA?
• Assertion Based Verification (ABV) Methodology Guidelines
SVA Language Overview
• Immediate assertions
• Concurrent assertions (with examples and applications)
– Basics (implication operator, formal args, severity levels, disable iff, etc.)
– Binding design module to property module
– Sampled value functions ($rose, $fell, $stable, $past)
– Operators (clock delay, consecutive, repetition, non-consecutive, goto)
– Sequence 'within', 'throughout', 'and', 'intersect', 'or', 'not', 'firstmatch'
– If… else
– System Functions ($onehot, $isunknown, etc.)/System Tasks ($asserton, $assertoff, etc.)
– Multi-Clocked properties
– Local Variables
– Embedding concurrent assertions in procedural code; calling subroutines; etc.

Cost: Free

Time: 10:00 am to 2:00 pm (Pacific Time)

Location:
Sunnyvale, CA
PlugandPlayTechCenter
440 N. Wolfe Rd. - Sunnyvale, CA 94085

Refreshments: Lunch will be provided

Event Link:http://www.aldec.com/Events/Event.aspx?companyeventid=46