Design for Testability and for Built-In Self Test

When: 12/08/2009 - 12/10/2009

Location: Los Angeles, CA United States Of America

This is really two courses combined into one. The first part, Design for Testability provides the guidelines necessary to improve circuit design from a test perspective. It includes simple and easy-to-implement ad-hoc testability guidelines. Then the course looks at more sophisticated structured approaches to testability that can be placed into ICs and boards. Special emphasis will be given to boundary-scan, the (JTAG) IEEE-1149.1. Analog circuit testability builds on the IEEE-1149.1 and is now the Mixed-Signal testability standard, designated as IEEE-1149.4. We examine this standard as well as the IEEE-1149.6 standard for AC Signal and transmission. We will look at other related standards in development, such as the IEEE-1532, IJTAG and SJTAG. The second part of the course will cover Built-In Test. Starting with classification of Built-In Test approaches, the course introduces the building blocks of built-in self test (BIST) architectures. The course then examines some of these architectures, including Random Test Socket (RTS), the Built-In Logic Block Observer (BILBO), the Cyclic Analysis Testing Systems (CATS), the Built-In Test Exerciser and Sensor (BITES), and others. BIT software is also covered and a discussion on BIT false alarms is included. Finally, a hierarchical approach to BIT is examined, which offers a reduction if not elimination of ATE in both a manufacturing and maintenance environment.

Additional information:
Website: http://www.besttest.com/Courses/00001-DFTBIST.cfm||Louis Y. Ungar