From graphene to MRAM
posted by Loring Wirbel on 10/02/2009 | comments 0
Do two instances constitute a trend? Less than a month after startup NuPGA promoted an FPGA based on a graphene memory element, EE Times tells us of a research project from the Montpellier Laboratory of Informatics, Robotics, and Microelectronics (LIRMM) in France, involving the use of MRAM cells in an experimental FPGA architecture.
Certainly, SRAM cells in FPGAs could stand to get a replacement, and flash memory does not seem to be that ideal substitute. Cases could be made for graphene, ferroelectrics, MRAMs, maybe even optical delay lines, for crying out loud. The French researchers make an interesting case for utilitarianism by opting for a thermally-assisted switching architecture that can cut voltage and power consumption in traditional magnetic field induction, by thermally heating a switch for each memory cell.
Thermal elements in modern MEMS structures are certainly not that radical, and this architecture could be brought to small-volume prototyping with relative ease. But LIRMM scientists are talking about stacking the MRAMs on CMOS and applying this 3-D structure to high-volume, small-feature-size manufacturing methods.
What I see going on with both NuPGA and the LIRMM group is that developers of unique memory concepts see the memory manufacturing field being closed to new ideas these days. They are certainly right, in that standalone MRAMs (as well as FRAMs, CAMs, etc.) face a commodity industry that has optimized processes for SRAM, SDRAM, and flash, and is not interested in taking a new concept into even limited production runs.
Therefore, since FPGAs are the booming industry these days, why not debut a memory architecture on an FPGA? Like I said in the NuPGA post, the problem with such a strategy is that it leapfrogs a necessary proof-of-principle step, and makes it even harder to prove a case to a foundry. If a foundry can’t manufacture a radical new FPGA in a cost-effective manufacturing process, the chances for such FPGAs to compete on a per-gate basis with standard FPGAs are slim.
The introduction of several new memory cells for unique FPGA architectures is certainly exciting, and sure to generate plenty of papers at ISSCC and IEDM. Whether any of these devices can make the case for high-volume manufacturing remains to be seen.
Post a comment
Lowest Power SERDES-Capable FPGA - ECP3 is the third generation high value FPGA from Lattice which offers the industry's lowest power consumption & price of any SERDES-capable FPGA device. It supports multi-protocol 3.2G SERDES with XAUI jitter compliance & DDR3 memory interfaces.
