RapidIO Coverage on EDN

1 - 10 of about 2396 results

Power: a significant challenge in EDA design

... is the gate-to-source voltage and VT is the threshold voltage. In older technologies, the leakage power was insignificant. As device sizes have decreased, leakage has become more significant in a number...
http://www.edn.com/article/521840-Power_a_significant_challenge_in_EDA_design.php

Baolab plans monolithic inertial MEMS

...GENEVA, Switzerland—Baolab Microsystems SL (Barcelona, Spain), a startup pioneering the creation of MEMS within the metal interconnect layers of CMOS wafers, has announced that it is planning to use its technology to build reconfigurable inertial measurement units (IMUs).Baolab has already developed a 3-D compass based on the technology and the company has said that it expects to modify the technology to also allow the inclusion of accelerometers and gyroscopes to enable the creation of IMUs. However, the company gave no timetable as to when it would produce mult-axis accelerometers or gyroscopes...
http://www.edn.com/article/521732-Baolab_plans_monolithic_inertial_MEMS.php

Robotic probes plumb brain's circuitry

... hope to build a catalog of necessary brain components and their interconnection method, which will then be used to build future brain-like computers.The brainchild of Georgia Tech doctoral candidate...
http://www.edn.com/article/521713-Robotic_probes_plumb_brain_s_circuitry.php

Mercury wins sensors processing subsystem contract with Raytheon

... that includes FPGAs, GPGPUS and GPPs, interconnected with high-speed switch fabrics. Ruggedized for harsh and mobile helicopter environments, the system will help improve mission effectiveness and flight safety at low altitude, in poor visibility and in hostile environments. The standards-based OpenVPX system is meant to allow for rapid future technology insertions either in terms of processing capabilities...
http://www.edn.com/article/521674-Mercury_wins_sensors_processing_subsystem_contract_with_Raytheon.php

New power semiconductor technologies challenge assembly and system setups

...) Connecting a cooler directly to DBC Using 2-side cooling Employing better interconnect technology Exploiting current at higher chip operating temperatures All of these methods are already in use today...
http://www.edn.com/article/521511-New_power_semiconductor_technologies_challenge_assembly_and_system_setups.php

Samplify solutions transform processing paradigms at DESIGN West 2012

... to this tool, which will show them how APAX can improve on their existing data-speed execution.Samplify's APAX technology accelerates high-performance-computing applications executing on computing clusters...
http://www.edn.com/article/521475-Samplify_solutions_transform_processing_paradigms_at_DESIGN_West_2012.php

IMEC offers 14-nm development kit

... the physical measurement of performance and power consumption and the first testing of the device, interconnect, process, and lithography assumptions. IMEC...
http://www.edn.com/article/521407-IMEC_offers_14_nm_development_kit.php

ACE AWARDS ULTIMATE PRODUCTS of 2011

... the same form factor as the company's MSO4000 scope. ANALOG ICs: 3LG family of CrystalFree CMOS oscillators (Integrated Device Technology) Traditional quartz-based oscillators are feeling the strain...
http://www.edn.com/article/521324-ACE_AWARDS_ULTIMATE_PRODUCTS_of_2011.php

ACE AWARDS DESIGN TEAM OF THE YEAR: Tilera's Tile-architecture design team

...;parlor." The Tilera team was left to start building the world's most advanced microprocessor technology on the porch and in the sun room, in the summertime, with no air-conditioning. So, for innovation, dedication...
http://www.edn.com/article/521318-ACE_AWARDS_DESIGN_TEAM_OF_THE_YEAR_Tilera_s_Tile_architecture_design_team.php

Intel reveals Ivy Bridge details

...Intel recently gave the first public look at Ivy Bridge, the first processors to use the company’s 22-nm trigate technology. Intel plans at least four major variants of the chip, which packs 1.4 billion transistors into 160 mm2 in its largest version. Ivy Bridge includes 20 channels of PCIe Generation 3 interconnect and a DisplayPort controller.The first Ivy Bridge chip, with as much as 8 Mbytes of cache memory, targets a range of desktop, notebook, embedded, and single-socket server systems. It integrates a memory controller and graphics, which now support DDR3L DRAMs and Microsoft DirectX 11...
http://www.edn.com/article/521206-Intel_reveals_Ivy_Bridge_details.php


1 - 10 of about 2396 results

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