2007 EDN DSP Directory: NeuroMatrix NM6403

NeuroMatrix NM6403

The NeuroMatrix NM6403 DSP is a dual-core application-specific DSP processor based on the NeuroMatrix Core (NMC). It provides scalable performance, a programmable operand width of 1 to 64 bits. This flexibility allows designers to trade precision for performance to suit their applications. The NM6403 processor includes a 32/64-bit RISC processor and a 1- to 64-bit vector coprocessor that supports vector operations with elements of variable bit lengths (US patent 6,539,368 B1).

The RISC core (VLIW) has a five-stage pipeline that operates with 32- and 64-bit-wide instructions. The NM6403 supports 32-bit immediate, base, indexed, and relative addressing. Each instruction usually executes two operations. Two 64-bit interfaces support SRAM, DRAM, and EDO DRAM and comprise two separate address-generation units that can address as much as 16 Gbytes. Each interface supports two memory banks and can support a "shared-memory" mode. Two DMA coprocessors transfer data between high-speed I/O-communication ports and external memory.

The NM6403 processor uses vector instructions to handle packets of as many as 32 64-bit data words. These instructions may define operations such as matrix-matrix, matrix-vector, or vector-vector multiplication, vector-vector addition/subtraction with saturation of results, block moving, and bit manipulation. The NM6403 has conditional branch, call, and return instructions.

The vector coprocessor, which has an SIMD (single-instruction-multiple-data) architecture, works on packed integer data comprising 64-bit blocks in the form of variable 1- to 64-bit words. The device supports vector-matrix or matrix-matrix multiplication. The Vector coprocessor's core looks like an array multiplier comprising cells that include a 1-bit memory (flip-flop) surrounded by several logical elements. Designers can combine the cells into several macrocells with two 64-bit programmable registers. These registers define the borders between rows and columns with macrocells.

Each macrocell performs the multiplication on variable-input words using preloaded coefficients and accumulates the result from the macrocells in the column above it. The columns simultaneously calculate the results in one processor cycle. For 8-bit data and coefficients, the vector coprocessor performs 24 MAC operations with 21-bit results in one 20-nsec processor cycle. The number of MAC operations depends on the length and number of words packaged into a 64-bit block. The engine's configuration can change dynamically during calculations. An application can start with maximum precision and minimum performance and dynamically increase performance by reducing the data-word lengths. To avoid arithmetic overflow, the NM6403 uses two types of saturation functions with user-programmable saturation boundaries.