2007 EDN DSP Directory: S6000

S6000

The Stretch S6000 family of software configurable processors targets high-performance video and wireless signal processing. The S6 Architecture offers three technology innovations: the second-generation Instruction Set Extension Fabric (ISEF), the Processor Array, and the Programmable Accelerator.

The S6 Architecture uses the Tensilica Xtensa LX dual-issue VLIW architecture which provides up to twice the performance of the previous processor architecture. The second generation ISEF (Instruction Set Extension Fabric) is embedded directly within the datapath of the Xtensa LX processor. The ISEF is a software configurable compute fabric that enables system designers to extend the processor instruction set and to define new instructions using C/C++ code. In addition to enhancements to the compute elements in the ISEF, 64 kbytes of distributed ISEF RAM (IRAM) with a dedicated high speed DMA channel were added to allow for the storage of data within the ISEF itself. Optimization of the ISEF compute elements and routing structures provide 300 MHz operation, three times the performance of the original architecture.

The Programmable Accelerator accelerates four compute-intensive functions and is accessed through a library of object-code calls. The Entropy Encoding accelerator function supports CABAC for H.264 Main Profile Encoding and CAVLC for H.264 Baseline Profile. The Motion Estimation accelerator performs sum-of-absolute-differences (SAD) calculations up to 64Giga-SADs/sec for Motion Estimation in algorithms such as H.264, MPEG4 and MPEG2. The Encryption accelerator supports commonly used encryption protocols, such as AES and 3DES. The Audio accelerator uses the Tensilica Xtensa HiFi-2 Audio Engine to support over 19 different audio codecs.

The Processor Array implementation allows architects to create systems of various compute levels. At the physical layer, each S6 device can interface with up to 4 other processors through dedicated 1.2 Gbyte/sec DDR interface banks. Above that layer, each S6 device has a dedicated processor network interface and switch circuitry to accommodate inter-processor communications. At the software layer, programmers create and assign tasks to processors, establish communication channels between processors, and even share resources between processors using a library of BIOS calls.

In addition, each S6000 member includes external memory support with a DDR2-667 SDRAM controller with 16- or 32- bit interface and a enhanced generic interface bus (GIB) for FLASH and other memory mapped peripherals. On-chip memory sub-systems include instruction and data cache, as well as a 64-kbyte block of SRAM. The 40 DMA controllers facilitate moving data on and off the devices with minimal processor interaction. The S6100 family member includes a four lane PCIe interface, Other integrated peripherals include triple speed Ethernet MAC, two multichannel Inter–IC Sound (I2S) interfaces, two-wire interface (TWI), serial peripheral interface (SPI), two UARTs, and general purpose I/O (GPIO).

There will be two development platforms available for the S6000 family. The first platform will showcase the single-chip capabilities for development of real-time video processing applications. The second will contain multiple S6000 family devices and will support the development of applications using the Processor Array. Both platforms will be fully supported within the standard Stretch development environment.