2008 EDN DSP Directory: Stratix III FPGAs

Stratix III FPGAs

Altera's new Stratix III family of low power, high-performance FPGAs introduce a new and innovative FPGA architecture that goes beyond optimized process and circuit techniques. Features like Programmable Power Technology and Selectable Core Voltage deliver a balance of performance, density, and power consumption. The PowerPlay features of the Quartus II design software automatically provide the lowest power consumption of a specific design while meeting performance requirements. The Quartus II design software features capabilities like Synopsys Design Constraint (SDC)-based timing analysis, incremental compilation, and a variety of system-level design tools such as DSP Builder and SOPC Builder.

Stratix III FPGA family consists of three family variants. The Stratix III L family provides balanced logic, memory and multiplier ratios for general-purpose applications. The Stratix III E family features memory- and multiplier-rich devices to target data processing applications. The Stratix III GX family includes embedded high-speed serial transceivers and extensive internal memory for targeting high-bandwidth applications.

Based on TSMC's 65-nm all-layer copper SRAM process, Stratix III devices have up to 112 DSP blocks enabling up to 896 18×18 FIR multipliers. Stratix III devices can perform various high-performance DSP functions for audio, automotive, wired and wireless communications, display, imaging and video, and military/aerospace applications. Stratix III FPGAs can be applied to complex systems such as WiMAX, 3GPP WCDMA, CDMA2000, voice over Internet protocol (VoIP), H.264 video compression and high-definition television (HDTV).