2008 EDN DSP Directory By Robert Cravotta, Technical Editor Peel away the layers of complexity and find the perfect digital-signal processor for your project using our comprehensive listing of digital-signal-processing resources, including software-programmable processors, programmable fabrics, IP (intellectual-property) blocks, and digital-signal controllers.
DIOPSIS 940HF is a dual-core processing platform for audio, communication and beam-forming applications, integrating a floating-point MagicV VLIW DSP and an ARM926EJ-S RISC microprocessor. The system combines the flexibility of the ARM926 RISC controller with the processing performance of the DSP oriented VLIW architecture of MagicV. The availability of a standard RISC and a DSP on the same chip make the D940HF suited for floating point applications with a significant need for complex domain computations like FFT and frequency domain phase-shift algorithms, requiring high dynamic range and maximum numerical precision. The ARM926 can be used for running operating systems and non critical and control code segments of the application while the MagicV DSP is available for the numerically intensive part of the processing.
ADVERTISEMENT
MagicV is a floating point VLIW processor of the Magic DSP family. It delivers 1 Giga floating-point operations per second (GFLOPS) and 1.5 Gops at a clock rate of 100 MHz. MagicV operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format for numerical computations, and on 16-bit integer data for addresses manipulation.
It is equipped with an AHB master port and an AHB slave port for system-on-chip integration. It has 256x40-bit data registers, 16x64-bit multi-field address registers to support DSP oriented addressing modes like circular and stride accesses, 10 arithmetic operating units, two independent Address Generation Units and a DMA engine. To sustain the internal parallelism, the data bandwidth through the Register File is 80 byte/cycle. The architecture is optimized to work in the complex domain. By activating all the computing units, mAgicV can produce one complex FFT butterfly per cycle. It also natively supports 2D vectorial arithmetic operations.
The Harvard memory architecture consists of an on-chip 2x8Kx40-bit data memory and an on-chip 8Kx128-bit program memory. Efficient usage of the program memory is achieved through a mechanism of program compression, performed by the software tool chain and supported by a hardware decompression engine. A program memory management unit supports a program space of 64Kx128-bit locations.
The MagicV DSP tool chain (including IDE, C compiler, linker, archiver, and a graphical JTAG debugger), thanks to the C-oriented DSP architecture, fully exploits the parallelism of the processor resources. Moreover, a library of 200 C-callable DSP routines, implementing optimised DSP algorithms (FFTs, filters, matrix computations, etc.) is distributed.
DIOPSIS 940HF consists of 48 Kbytes internal memory integrated with peripherals such as: External Bus Interfaces (EBI) with dedicated controllers for SDRAM, static memory, SmartMedia and NAND Flash, CompactFlash; USB 2.0 Full Speed (12 Mbits per second) host/device; 10/100 Ethernet MAC; four SSC; three USART; two SPI; Time Counter (TC); two TWI; two CAN; Multimedia Card Interface for PDMA, MMC and SDCard.
The ARM926 supports 16-bit Thumb subset of the most commonly used 32-bit instructions. This gives 16-bit code density (saving memory area and cost) coupled with a 32-bit processor performance. Evaluation kits for the Diopsis 940HF and development tools (also including Linux porting for the platform, drivers and libraries) are available.
2008 EDN DSP Directory