A lot of product designs face a roadblock, but few face the number of obstacles that Steve Douglass, Suresh Menon, and the Xilinx Virtex-5 LXT design team did. The FPGA design included a move to a 65-nm process, necessitated a balance of programmability and hard-IP (intellectual-property) features, and realistically required a solution to ballooning dynamic-power consumption. The result is a chip that has more than a billion transistors, yet, according to Xilinx, it realized a 35% reduction in dynamic power relative to earlier 90-nm designs.

The Virtex-5 LXT team included more than 200 engineers organized into groups called "Centers of Excellence," with each group focusing on a specific aspect of the new architecture. Product planners met with hundreds of system designers to get input on the new architecture. The company claims the result is 30% higher performance and 65% higher logic density.

The Virtex-5 LXT design leads a trend of balanced programmability and fixed functions. The chip includes built-in hard-IP blocks for what Xilinx claims are the two most popular serial-I/O standards: PCIe (PCI Express) and Gigabit Ethernet. The hardened PCIe endpoint block saves users as many as 10,000 look-up tables and 2W of power compared with soft-IP-core implementations. The company points to industry research suggesting that PCIe and Gigabit Ethernet will account for approximately 80% of all I/O-port shipments in 2009, making a case for hardening these blocks on the FPGA, thus saving logic resources and consuming lower power than soft-IP approaches.