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2007 EDN Microprocessor Directory: Different strokes
By Robert Cravotta, Technical Editor
Our 34th Annual Microprocessor and Microcontroller Directory presents you with a palette of processing options and development tools for your project. Includes details on hundreds of devices and cores from nearly 70 vendors.
2007 EDN Microprocessor Directory: Our 34th Annual Microprocessor and Microcontroller Directory presents you with a palette of processing options and development tools for your project. Includes details on hundreds of devices and cores from nearly 70 vendors. By Robert Cravotta, Technical Editor

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LatticeMico32

The LatticeMico32 is a configurable 32-bit Harvard architecture "soft" microprocessor core for Lattice Field Programmable Gate Array (FPGA) devices. By combining a 32-bit wide instruction set with 32 general-purpose registers, the LatticeMico32 provides the performance and flexibility for many applications. The core employs a RISC instruction architecture. The LatticeMico32 System Development Tools supports processor platform definition, software development, and debug. The LatticeMico32 is available as source code under the Lattice open IP core license, thereby providing visibility, flexibility, and portability at no charge.

Designers can use the LatticeMico32 system tools to implement the LatticeMico32 soft microprocessor and attached peripheral components in a Lattice FPGA. It is based on the Eclipse C/C++ Development Tools (CDT) environment. The LatticeMico32 System consists of the MSB (MICO system builder) and the C/C++ SPE (software project environment) and debugger that combine with ispLEVER to coordinate the building of an embedded processor system on an FPGA device and write the software to drive it. The generated LatticeMico32 core and selected peripheral component HDL codes are available through a unique open IP core licensing agreement, while the GNU-based compiler, assembler, linker and debugger are licensed under the GNU GPL agreement.

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The MSB can generate a platform description and associated HDL for hardware implementation, choose peripheral components to attach to the LatticeMico32, and specify the connectivity between peripheral components. The C/C++ SPE and debugger support development and simulation (instruction set simulator) of the code that will operate on the platforms created with MSB. It uses a command line interface to direct the compiler, assembler, linker, and debugger tools. The Lattice GNU-based compiler tools include appropriate compiler, assembler, linker, and debugger as needed.

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