Post a Comment
Analog Devices Inc ADSP-218x and ADSP-219x
-- EDN, 3/29/2001
The ADSP-21xx family executes all instructions in one cycle. Each family member extends the code compatibility of the ADSP21xx family. The processors feature an algebraic programming syntax and can execute multiple operations per cycle. Family members have X and Y DAGs (data-address generators) and separate program and data buses.Analog Devices opted for a 16-bit-wide data word and a 24-bit-wide instruction word. The wider instruction word lets the device use more complex instructions and offers more flexibility than 16-bit operation code. The ADSP-21xx family integrates as much as 2 Mbits of SRAM around the DSP core to increase data-transfer efficiency. It also integrates DMA ports that connect to external hosts or external memory. These bidirectional, byte-wide ports can directly access as much as 4 Mbytes of external memory for off-chip storage of program overlays and or data tables. The ADSP-219x DSP supports as many as 16M words of addressable memory space with 24 bits of addressing width. It also provides two 40-bit accumulators and a 40-bit shifter, which help with overflow.
Addressing modes: The ADSP-21xx family supports immediate, register-direct, memory-direct, and register-indirect addressing modes. The ADSP-219x adds register, indirect-post-modify, immediate-modify, and direct- and indirect-offset addressing modes. Each address generator supports as many as four circular buffers, each with three registers. The ADSP-219x supports as many as 16 circular buffers using a DAG shadow register and a set of base registers for additional circular-buffering flexibility.
Special instructions: The ADSP-21xx can conditionally execute most instructions. A "do-until" command establishes a sequence of instructions that can be arbitrary in length and nested four deep for repeat operations. The ADSP-219x allows as many as eight nesting levels. In addition to the standard arithmetic and logic instructions, the ALU (arithmetic-logic unit) supports division primitives. Because the ADSP-21xx is nonpipelined, it incurs no penalties for jumps and calls.
Support: Software- and hardware-development tools include the VisualDSP and VisualDSP++ IDE, an evaluation kit, and a serial-port emulator, for development, debugging, and deployment. The EZ-Kit Lite contains an evaluation board and software that provides developers a cost-effective method for initial evaluation of the ADSP-218x DSP family architecture. The ADSP-218x EZ-ICE (in-circuit emulator) provides an easier and more cost-effective method for engineers to develop and optimize DSP systems, shortening product-development cycles for faster time to market. VisualDSP++ integrates an RTOS kernel, a C++ compiler, and a debugger into an easy-to-use environment.
