Altera

-- EDN, 8/17/2000

When Altera entered the SRAM-based programmable-logic business in 1992, the company had to ensure that it didn't step on any of the patent land mines left by FPGA originator and biggest competitor Xilinx. Altera marketers also wanted to exploit the company's dominant CPLD heritage. They wanted to promote the fact that the company's routing architecture, unlike Xilinx's devices of the time, consisted of a high percentage of fast, long signal lines that ran across the chip, thereby making the signal timing more predictable, or more CPLD-like.

As a result, you'll never find the acronym FPGA in any of Altera's literature, even though the rest of the world knows the chips as FPGAs. Altera prefers to call its parts LUT-based programmable-logic devices. A long-line, routing-dominated FPGA architecture provides another benefit in addition to timing predictability; Altera has consistently implemented on-chip redundancy, particularly at the early stages of process and device production, to improve yields.

Altera's initial FPGA architecture, the Flex 8000 series, was quickly superseded by the Flex 10K family, which added embedded SRAM arrays that the company calls EABs (embedded array blocks). Subsequent iterations of Flex 10K have migrated to smaller lithography processes with additional metal routing layers. With the Flex 10KE generation, Altera made significant architectural improvements, including the incorporation of PLLs and true dual-port SRAM capability. Previously, the company emulated dual-port RAM by requiring you to use twice as much single-port memory.

From the Flex 10K architectural foundation, Altera has taken its FPGA product line in three directions, all based on a common, essentially unchanged LAB (logic-array-block) structure. Flex 6000, the Flex 8000 successor, targets moderate-density and -performance designs that require no on-chip memory or esoteric packaging. Altera eliminated the Flex 10K PLLs and decreased the amount of global signal routing on Flex 6000 from that of the Flex 10K. Instead, the Flex 6000 substitutes dedicated local LAB-to-LAB and LAB-to-I/O-buffer interconnect.

Apex 20K, which Altera initially called Raphael, includes as many as four on-chip PLLs. The device family also includes larger and more numerous EABs and flexible I/O buffers that support numerous protocols and electrical standards. As with Xilinx's chips, Altera's devices' EABs are the key factors behind the vendor's claims of exponentially growing gate counts. If you can use all that memory: great. If not, you won't come close to squeezing into one chip the design sizes that Altera's marketing might indicate are possible.

Apex 20KE (Picture), the latest iteration of the product family, enables you to use the EABs not only for implementing single- and dual-port RAM and FIFOs, but also for very small CAMs. The recently introduced Acex 1K family is basically Flex 10KE built on a smaller lithography process that is optimized for low cost. Like Flex 6000, Acex comes in smaller gate counts and with more restricted, less expensive packaging options than its Flex 10K and Apex 20K big brothers. Acex 1K parts run at a 2.5V core voltage, and upcoming Acex 2K parts (probably based on the Apex 20K architecture) will operate at 1.8V.

By year-end, Altera hopes to be sampling its first hybrid ASIC-plus-programmable-logic devices, incorporating ARM and MIPS cores. The company also hopes to gain access to PowerPC via a licensing agreement with Motorola. Altera has also developed an optimized 8- and 16-bit RISC architecture it calls Nios, which aims to reside in FPGA logic instead of in ASIC gates. Over time, Altera plans to port Nios to its Apex 20K, Acex 1K, and subsequent architectures, along with its other internally developed and partner-developed cores, such as 64-bit/66-MHz PCI. The same Max+ software you'd use to design with Altera's CPLDs also supports Acex 1K and Flex FPGAs. For Acex 2K and Apex devices, you'll want to fire up Altera's more advanced Quartus development-tool environment, along with the SignalTap logic analyzer.