Altera

-- EDN, 8/17/2000

In the late 1980s, Alterapioneered the concept of the CPLD, a device with numerous logic blocks, each consisting of a PAL- or SPLD-like group of macrocells. These logic blocks interconnected to each other and the outside world via a fully or partially populated switch matrix. Altera's early CPLDs used PROM or EPROM cells as switch-configuration elements, but the company's Max devices have migrated to in-system-programmable EEPROM technology.

Max 7000 (Picture) is the primary workhorse of today's Altera CPLD-product line, and the architecture has remained essentially unchanged through multiple process evolutions. Smaller semiconductor lithographies often translate not only to lower cost per macrocell but also to higher speed, lower operating voltage and power consumption, and higher macrocell counts. Along the way, Altera has fine-tuned the Max 7000 in numerous ways. Perhaps the most significant tweak is the addition of in-system programming beginning with the 5V S series. The 3.3 and 2.5V variants also include this in-system programming. Altera is also particularly proud of its Multivolt I/O technique, in which the I/O buffers drive output and handle input voltages both lower than and exceeding the device's core operating voltage for no-glue system interfacing.

In an attempt to radically grow the macrocell capacity of its CPLDs, Altera introduced the Max 9000 family in 1994. This CPLD architecture migrates from a monolithic logic-block-to-block interconnect matrix to a multistage approach. This new approach is reminiscent of the company's Flex devices and more generally of any segmented routing FPGA. The advantage of a hierarchical interconnect structure is that, because it is distributed throughout the device, it doesn't exponentially grow with increasing macrocell and—therefore—logic-block count, as a global matrix tends to do.

The disadvantage of a hierarchical approach, though, is that pin-to-pin timing and logic-block-to-block timing depend on placement and are therefore unpredictable. Performance predictability and the ability to more easily implement logic circuits with many product terms and comparatively fewer registers have always been key advantages of PALs and PLDs over FPGAs. Note from Table 2 that the Max 7000 family, which has undergone aggressive cost reductions, now comes close to matching the logic complexity of the largest Max 9000 device and at a lower price per macrocell.

Altera has also recently introduced its Max 3000A product family. This introduction may be in response—at least partially—to the aggressive prices of upstart CPLD-replacement vendor Clear Logic. Altera constructs today's Max 3000A parts from the same die that it uses for its 3.3V Max 7000 devices. However, the company tests Max 3000A parts to relaxed specifications, allowing higher power consumption. Altera offers the parts with fewer packaging options and doesn't claim to support all of the Max 7000 features. Don't be surprised to see the company develop tailored Max 3000 chip designs, such as the upcoming 2.5V Max 3000B.

Design-tool support comes from Altera's Max+Plus II development software, which is available in both single- and floating-node versions and for multiple operating systems. Altera's tool sets—as with those of all the vendors in this directory—come in multiple versions; support various families of products and devices within each product family; and offer multiple design-entry, simulation, synthesis, fitting, and programming options.