Microprocessors

-- EDN, 12/9/1999

Processor packs x86 compatibility with loads of peripherals. The ÉlanSC520 integrates a 133-MHz Am5x86 processor core with 16 bytes of write-back cache, PC/AT-compatible peripherals, a synchronous-DRAM (SDRAM) controller, and a PCI-bus interface. The SDRAM controller allows the device to access one to four mixed banks of SDRAM using programmable cycle timing. The 33-MHz, 32-bit PCI-bus interface supports as many as five external PCI masters. Other features include a general-purpose-bus interface, two 16550 UARTs, a synchronous serial interface that supports SPI and Microwire protocols, and AMDebug technology. The device is available in a 388-pin plastic BGA package, operates at 100- and 133-MHz with a 2.5V supply, and sells for $38 (10,000). AMD, 1-800-222-9323, www.amd.com.

Floating-point DSP breaks $5 barrier. Texas Instruments has introduced the $5 (100,000) TMS320VC33 floating-point DSP, leapfrogging the $10 price barrier that Analog Devices set last year with its $10 (100,000) SHARC-based 21065L floating-point DSP. The C33 contains 1 Mbit of RAM, has the same peripherals as the TSM320C31, and comes in a 144-pin TQFP. The new device runs at 120 MHz; a 150-MHz version sells for $8. Texas Instruments, 1-800-477-8924, ext 4500, www.ti.com/sc/c6000.

Philips breathes new life into 80C51. The 87LPC764, the first device in Philips' 51LPC family, contains 4 kbytes of one-time-programmable program memory and 128 bytes of SRAM. It also incorporates two analog comparators. The device is available in 20-pin SOIC and PDIP packages and costs $1.10 (10,000). Philips also offers the Link-51 evaluation kit, which includes emWare's (www.emware.com) Internet-capable software, for $79.95. Link-51 comes with a demonstration board and a fully operational demonstration version of emWare's Embedded Micro Internetworking Technology (EMIT) gateway software. Philips has programmed the 87LPC764 devices in the kit with the emMicro (firmware that enables a user to control the device through the EMIT emGateway via a standard Web browser). Philips Semiconductors, 1-800-447-1500, www.semiconductors.philips.com.

Motorola DSP packs tons of memory. For multichannel communication and networking systems, the new 24-bit DSP56311 packs 3 Mbits of single-cycle SRAM. The chip also contains the company's enhanced filter coprocessor, which allows the DSP to process filter algorithms in parallel with core operation. Other features include a 56-bit barrel shifter, a six-channel DMA controller, two enhanced synchronous serial interfaces, an 8-bit parallel host interface, a serial communications interface with a baud-rate generator, a triple timer module, and as many as 34 programmable general-purpose I/O pins. The device comes in a 196-bump PBGA, operates as fast as 150 MHz at 1.8V, and sells for $56 (10,000). Motorola, 1-800-441-2447, www.motorola-dsp.com.

Technosoft revs up DSP for motor control. Technosoft has used Texas Instrument's TMS320C24x core to develop its MotionChip, a C240 that the company has ROM-coded with motor-control algorithms for voltage, torque, speed, or position control. The MotionChip supports most industrial motors and single-motor or multimotor applications. It uses Technosoft's Motion Language (TML) commands to initiate control algorithms and pass parameters for system customization. The chip also operates in slave mode for multiaxis applications with distributed intelligence. Technosoft provides high-level graphical tools for software setup and motor-control-algorithm tuning. The Motion Chip costs $35.95 (1000). Technosoft, +41 91 976 0501, www.technosoft.ch.

Instruction language allows you to integrate your custom logic. Tensilica's Xtensa architecture is a configurable RISC processor that allows you to define new mnemonics, operation codes, and the associated computational functions. The Tensilica Instruction Extension (TIE) language, a subset of Verilog, allows you to integrate your custom logic into the RTL for the base processor as well as the compiler/simulator suite. Unlike most RISC architectures, Xtensa instruction lengths are 16- and 24-bits wide; the most significant bit in each operation code identifies the instruction size. Tensilica has implemented an overlapping windowed-register scheme, also known as variable-overlap register windows. The register windows allow the compiler to automatically choose the optimal shift of the register window on each procedure call. You can overlap procedures by zero, four, eight, or 12 registers using a pointer that software can increment or decrement on each call or return. This register pointer wraps around in circular fashion, and the CPU generates appropriate underflow and overflow exceptions when it uses a wrapped register or a return re-exposes saved registers. Tensilica, 1-408-986-8000, www.tensilica.com.

MIPS64 5Kc is the first 64-bit synthesizable processor core. The MIPS64 5Kc provides system and ASIC designers an ability to customize the core and integrate it with custom logic, memory, and on-chip peripherals. A MIPS64 5Kc license includes training, gate-level simulations, functional verification suite, documentation, RTL, reference boards, and software access. The 5Kc incorporates a six-stage pipeline that performs single-cycle MAC instructions, static branch prediction, and speculative instruction fetching. The core includes an FPU and coprocessor interface, and a user-programmable cache controller. This architecture supports the MIPSR5000/R4000 TLB and privilege-mode extensions. MIPS Technologies, 1-650-567-5000, www.mips.com.

Network processor manipulates and transports data traffic. Intel's IXP200 is a network processor that packs in six RISC communication engines managed by a StrongARM SA1 core. Each RISC engine can run four application threads and has its own set of 128 registers and 128 I/O transfer registers, as well as four program counters to avoid context switching penalties. The IXP1200 includes an SRAM controller that improves memory access time by queuing reads and writes together and works with the threading capability to minimize stalls while waiting for data. Level One Communications, 1-916-855-5000, www.level1.com.

SH4 RISC Core is Windows-compatible. The SH7751 combines Hitachi's two-way superscalar SH4 RISC core with a PCI V2.1 interface, a dedicated four-channel DMA controller for transfers across the PCI bus, and five 32-bit timers. This Windows CE-compatible device operates from 133 MHz and 1.5V to 167 MHz at 1.8V and delivers as little as 240 mW of power consumption. The core includes an arithmetic floating-point accelerator and on-chip debugging capabilities via a JTAG-compatible interface. Hitachi, 1-800-448-2244, www.hitachi.com.

HDLC processor combines hardware and software technologies. The TS704 edge processor performs HDLC processing on 672 DSO, 84 DS1, or three 52-Mbit high-speed serial link (HSSL) channels. The 12-million transistor chip comprises four SPARClet-based RISC cores, four integrated communications coprocessor HDLC engines, 16 serial links (52 Mbps each) a PCI 2.1 interface, a synchronous DRAM controller, a debugging support unit, a JTAG test port, a 10-pin peripheral interface adapter, and six timers. The chips also incorporate T.sqware-provided microcode that handles low-level network processing. Price is $1250. T.sqware, 1-408-327-5900, www.tsqware.com.