FROM EDN EUROPE: Design FPGAs in hardware/software tool set

Xilinx recently announced the Virtex-II Pro family of devices, which embeds as many as four PowerPC 405 cores; the company claims that this family is the only high-end FPGA one that it will develop. The family now has some extra parts, but all of the new ones have at least one core. Xilinx claims that the cores' area is so small that there is no benefit to producing a chip without them; if you don't want them, you need not use them.

To support the series, Xilinx has introduced Version 5.1i of its ISE (Integrated Software Environment) design software and Version 5.1i of ChipScope Pro, the on-chip-logic-analyser feature of its tool set as the first elements in a framework of tools for system-level design on programmable chips. This product integrates a bus-analyser core, a core-insertion tool, and a system analyser.

ISE 5.1i compiles at 200,000 gates/minute and derives a 15% device-performance acceleration from algorithmic tuning. It adds the facility to do incremental design revisions, recompiling only altered sections, and has a pinout- and area-constraint editor to control pin assignment. An architecture tool assists with the design of complex functions, automatically outputting HDL models of the functions it creates. Routines assist with clock management and with setting up multigigabit transceivers. You can also improve your reuse with a macro tool that captures relative placement data, but not routing, so that you can place the same block in another location or device.

The ChipScope tool is key in Xilinx's objective of moving toward an integrated system-level, hardware/software co-design environment for its FPGAs. With the necessary on-chip hardware support, it can observe any node with logic- and bus-analysis facilities. For software development, it also supports real-time instruction trace, implementing trace commands from "partner" products, such as debuggers, using the IBM standard-trace commands. You can therefore implement an architectural-synthesis design flow in which you build, not model, the structures you are designing and evaluate them in real time; Xilinx proposes later extending the coverage of the tool to a higher level, hierarchical approach.